aarch64.risu: add C3.6.25 Floating-point data-processing (1 source)

this adds C3.6.25, including

FMOV (register), FABS (scalar), FNEG (scalar), FCVT,
FSQRT (scalar), FRINT (scalar)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risugen: change floating point randomization for aarch64

generate "interesting" values for aarch64 as well,
in the same way as we do for ARM.

Also disable use of LD1 to load 4 regs at a time, for now,
and replace with LDP Qn, which loads only 2 regs at a time.
As LD1 is implemented and stable, we can switch back to use it.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>