hdl: Firmware v2.13 - Connects PLX reset output line (l_reset_n_i) to FPGA logic.

This is to reset the FPGA when the computer is reset and avoid interrupts being
generated during reboot.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cbmia@78736 0a99fbf0-06a5-4c52-8a11-fe70044ee989
Update README with git-svn command to commit in svn.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk/fpga/cbmia@78737 0a99fbf0-06a5-4c52-8a11-fe70044ee989