xilinx_axienet: Setup PHY reg to Marwell 88e1111

The only one reason is that axi_ethernet u-boot drivers
require this PHY IDs not to fail.

Signed-off-by: Michal Simek <monstr@monstr.eu>
HACK: faked arm co-processor cycle timer

Nasty hack to overcome ticket 1343. A more complete solution should be
implemented that conforms to the spec for this timer. This one will really
only work for differential timing (i.e. for sleep()). The absolute value
of the timer will be garbage. Assumes a 1GHz clock rate (i think)

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
HACK: sd.c: mirrored opcodes for sd styles

The xilinx test cases provided use a mix of sd/mmc and spi styles commands.
The sd model expects it to be all one or the other. I have mirrored some of
the spi style command for sd/mmc mode to get xilinx test case to work.

This patch is not upstreamable (unless we later determine its actually a
shortcomming in sd which i dont think it is just yet - need to look into
it)

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Zynq: change phy address to 7

Changed phy address to 7 as that matches the Xilinx ZC702. THe previous value
was for the pre-silicon emulation platform.

Signed-off-by: Jason Wu <jason.wu@petalogix.com>
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
block: Removed coroutine ownership assumption

The block layer assumes that it is the only user of coroutines -
The qemu_in_coroutine() is used to determine if a function is in one of the
block layers coroutines, which is flawed. I.E. If a client (e.g. a device or
a machine model) of the block layer uses couroutine itself, the block layer
will identify the callers coroutines as its own, and may falsely yield the
calling coroutine (instead of creating its own to yield).

AFAICT, there are no conflicts in the QEMU master here yet, but its kind of an
issue, as anyone who comes along and used coroutines and the block layer
together is going to run into some very obscure and hard to debug race
conditions.

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
sd: P Brook hack to make sd spi work for stellaris

To make the stellaris SPI test vector work.

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
usb/ehci: Put RAM in undefined MMIO regions

Just put RAM regions in the unimplemented spaces in the MMIO region. These
regions have undefined behaviour, but this at least stops QEMU from segfaulting
when the guest bangs on these registers (and sucessfully fakes reading and
writing the registers with no side effects).

---CHANGELOG---
changed from v1:
greatly simplified implementation.
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
dma: Define dma_context_memory and use by default

Define a new global dma_context_memory which is a DMAContext corresponding
to the global address_space_memory AddressSpace. This can be used by
sysbus peripherals like sysbus-ohci which need to do DMA.

[PC] Use this dma context by default if NULL is passed to the dma API for
DMAContext *dma

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm_boot: added linux switch

Added a switch to tell the bootloader that the image is linux and should be
bootstrapped as such. This is needed to boot an elf that is linux.

Syntax would be:

qemu-system-arm ... -kernel linux.elf -machine linux=on

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
HACK: silent fail qdev_set_nic_properties

Just nop if qdev_set_nic_props() fails rather tahn exit(1).

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: arm_gic: change default number of IRQs

Change the default to 96 interrupts to match a9mpcore default.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm_mptimer: autodetect the number of CPUs

If num_cpu is not set automatically detect the number of CPUs and set it.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm_gic: autodetect the number of CPUs

If num_cpu is not set automatically detect the number of CPUs and set it.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
zynq_slcr: autodetect and link up CPUs

If CPU links are not set automatically detect the system CPUs and just hookup
automatically.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
arm_boot: Allow direct passing of a DTB

Allow machine models to pass in an already modified DTB to the bootloader.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
hw: zynq_slcr.c: Configure MIO for QSPI based on DTB

The first QSPI MIO [2-6] reg is only configured if a child node is found.
Set the second QSPI MIO [8-13] reg, if the is-dual property is set to 1.
The MIO regs are set to 0x202 (QSPI and LVCMOS18)

Signed-off-by: Jason Wu <huanyu@xilinx.com>

Ammended by Wendy:

zynq_slcr: Modify MIO settings for QSPI based on lastest u-boot

The following patch to u-boot change how to detect whether it is dual qspi
flash:

commit feac0114fa2783aaaa3b5513a47262e461e354d1
Author: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com>
Date:   Thu Mar 14 17:59:13 2013 +0530

    spi: zynq: Move qspi MIO detection code into slcr

    This patch provides a support for the qspi MIO runtime
    detection code through slcr driver.

    Now, slcr driver is capable to get the status of specific MIO
    pins by taking an @periph name as an argument.

    Currently added qspi0, qspi1_cs and qspi1 as @periph names.

This patch is to update QEMU MIO settings based on this patch.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
i2c: Autoconnect function.

Function to automatically connect all children nodes to a i2c bus.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: configure: Dont build with --warn-common

This causes amazing amounts of build log spam when building on the Xilinx
redhat machines. Disabled.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: Force enable libfdt

Xilinx QEMU makes no sense without libfdt, Force enabled.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
HACK: target-arm: Harcode the SCU offset

Becuase the QOM framework to drive this from a property isnt there yet.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>