Corrected a major bug in the operation timing of the load literal instruction.   There had been a mismatch between the data availability (cycle 0) and the microcode to drive the update or TOS (cycle 1).  Moved the data availability to cycle 1 by taking advantage of the fixed PC increment of 1 byte and using the ordinary SRAM memory channel.
Removed the data_plus output from SRAM Controller as it is no longer needed