automake: handle expat version pre 2.1

Commit aec20d66d9d13e0acd6a7199b63e1383e1e9900a
(automake: properly handle non-default expat installation),
assumed that up-to date distributions use a recent version
of expat that handles security vunerabilities CVE-2012-1147
and CVE-2012-1148. Seems like this is not always the case
and they prefer to backport only the fix, rather than use
the updated library.

This commit adds a default case -lexpat whenever expat is
not found, while properly handling expat.pc if present.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71022
Reported-By: Bryce Harrington <b.harrington@samsung.com>
Reported-By: Vinson Lee <vlee@freedesktop.org>
Tested-by: Bryce Harrington <b.harrington@samsung.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
i965: Compute the node's delay time for scheduling.

This is a step in doing scheduling as described in Muchnick (p538).  A
difference is that our latency function is only specific to one
instruction (it doesn't describe, for example, the different latency
between WAR of a send's arguments and RAW of a send's destination), but
that's changeable later.  We also don't separately compute the postorder
traversal of the graph, since we can use the setting of the delay field as
the "visited" flag.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Prefer more-critical instructions of the same age in LIFO scheduling.

When faced with a million instructions that all became candidates at the
same time (none of which individually reduce register pressure), the ones
on the critical path are more likely to be the ones that will free up some
candidates soon.

shader-db:
total instructions in shared programs: 1681070 -> 1681070 (0.00%)
instructions in affected programs:     0 -> 0
GAINED:                                40
LOST:                                  74

Fixes indistinguishable-from-hanging behavior in GLES3conform's
uniform_buffer_object_max_uniform_block_size test, regressed by
c3c9a8c85758796a26b48e484286e6b6f5a5299a.  Given that
93bd627d5a6c485948b94488e6cd53a06b7ebdcf was unlocked by that commit, the
net effect on 16-wide program count is still quite positive, and I think
this should give us more stable scheduling (less dependency on original
instruction emit order).

v2: Comment suggestions by Paul

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70943
Reviewed-by: Paul Berry <stereotype441@gmail.com>
radeon/llvm: Specify the DataLayout when running optimizations

Without DataLayout, a lot of optimization passes aren't run and the ones
that are don't work as well.
clover: Don't install headers when using the icd

The ICD loader should be responsible for installing headers.

Reviewed and Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
radeonsi: Allow longer intrinsic names

Fixes a boat load of Piglit tests for me, which crashed like fdo#70913
before.

Thanks to Michel Dänzer for the tip.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70913
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
i965/fs: Update an ancient, wrong comment about reg_offset.

This hasn't been true since SIMD16 mode was added.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Split "find what MRFs were used" to a helper function.

I'm going to need to reuse this for fixing register spilling on SIMD16.
Note that BRW_MAX_MRF is 16, which is the same as BRW_MAX_GRF -
GEN7_MRF_HACK_START.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Fix broken register spilling debug code.

Now that reg spilling generates new vgrfs, we were looping forever if you
ever turned it on.

Instead, move the debug code into the register allocator right near where
we'd be doing spilling anyway, which should more accurately reflect how
register spilling occurs in the wild.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Exit the compile if spilling would overwrite in-use MRFs.

I believe this will never happen in SIMD8 mode, but it could for SIMD16
when we fix it.

v2: Fix off-by-one in my register counting comment (caught by Paul).

Reviewed-by: Paul Berry <stereotype441@gmail.com> (v1)
i965/fs: Fix register spilling for 16-wide.

Things blew up when I enabled the debug register spill code without
disabling 16-wide, so I decided to just fix 16-wide spilling.

We still don't generate 16-wide when register spilling happens as part of
allocation (since we expect it to be slower), but now we can experiment
with allowing it in some cases in the future.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Fix register unspills from a reg_offset.

We were clearing the reg_offset before trying to use it.  Oops.  Fixes
glsl-fs-texture2drect with the reg spilling debug enabled.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE

I'm going to be introducing gen7 variants, and the previous naming was
going to get confusing.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Use the gen7 scratch read opcode when possible.

This avoids a lot of message setup we had to do otherwise.  Improves
GLB2.7 performance with register spilling force enabled by 1.6442% +/-
0.553218% (n=4).

v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul).

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Add is_null() method to fs_reg.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Add reads_flag() and writes_flag() to fs_inst.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Use reads_flag and writes_flag methods in the scheduler.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Don't emit null MOVs in CSE.

We'd like to CSE some instructions, like CMP, that often have null
destinations. Instead of replacing them with MOVs to null, just don't
emit the MOV.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
i965/fs: Perform CSE on CMP(N) instructions.

Optimizes

      cmp.ge.f0(8)  null     g45<8,8,1>F  0F
(+f0) sel(8)        g50<1>F  g40<8,8,1>F  g10<8,8,1>F
      cmp.ge.f0(8)  null     g45<8,8,1>F  0F
(+f0) sel(8)        g51<1>F  g41<8,8,1>F  g11<8,8,1>F
      cmp.ge.f0(8)  null     g45<8,8,1>F  0F
(+f0) sel(8)        g52<1>F  g42<8,8,1>F  g12<8,8,1>F
      cmp.ge.f0(8)  null     g45<8,8,1>F  0F
(+f0) sel(8)        g53<1>F  g43<8,8,1>F  g13<8,8,1>F

into

      cmp.ge.f0(8)  null     g45<8,8,1>F  0F
(+f0) sel(8)        g50<1>F  g40<8,8,1>F  g10<8,8,1>F
(+f0) sel(8)        g51<1>F  g41<8,8,1>F  g11<8,8,1>F
(+f0) sel(8)        g52<1>F  g42<8,8,1>F  g12<8,8,1>F
(+f0) sel(8)        g53<1>F  g43<8,8,1>F  g13<8,8,1>F

total instructions in shared programs: 1644938 -> 1638181 (-0.41%)
instructions in affected programs:     574955 -> 568198 (-1.18%)

Two more 16-wide programs (in L4D2). Some large (-9%) decreases in
instruction count in some of Valve's Source Engine games. No
regressions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
st/draw: silence Mingw warning in pointer_to_offset()

Fixes "warning: cast from pointer to integer of different size" for
64-bit builds.