Merge remote-tracking branch 'upstream/master'
Merge remote-tracking branch 'upstream/master'
Merge remote-tracking branch 'upstream/master'
Merge remote-tracking branch 'upstream/master'
Merge remote-tracking branch 'upstream/master'
Merge remote-tracking branch 'upstream/master'
[CORE] Rename vmm_guest_physical_xxx() APIs to vmm_guest_memory_xxx() APIs

The original vmm_guest_physical_xxx() APIs were meant to access guest RAM, guest ROM and guest devices but for accessing guest devices we need to be in normal VCPU context.

To simply the situation we provide vmm_guest_memory_xxx() APIs for accessing guest RAM and guest ROM only.

The vmm_guest_memory_xxx() APIs will internally use vmm_host_memory_xxx() APIs to do cacheable & bufferable access guest RAM and guest ROM.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Poll for online CPUs before initializating modules

Xvisor modules might use SMP IPIs or might have per-cpu context so, poll for online CPUs before vmm_modules_init() in-order to make sure that correct number of online CPUs are visible to all modules.

Signed-off-by: Anup Patel <anup@brainfault.org>
[DOCS] Update docs/arm to reflect all supported ARM host

Signed-off-by: Anup Patel <anup@brainfault.org>
[DRIVERS] i.MX: add low level support for i.MX serial port.

This only adds the required i.MX support to get it working in
polling mode at Xvisor startup.

More complete support will be added later.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] i.MX: Add AVIC interrupt controller support.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] i.MX: Add EPIT timer support.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] i.MX: Add i.MX31 support and KZM boad support

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Fix cache operations for ARMv6 host CPUs

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] Force ARM Errata 411920 for BCM2835 SOC

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Make sure lock is released when returing from cpu_mmu_l2tbl_alloc()

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Fix hard-coded weight in arch_delay_loop_cycles()

With recent implementation, the hard-coded weight used for converting delay loop count to delay loop machine cycles has changed (Don't know why ??).

I have tested thoroughly on BeagleBoard-xM & Hackberry to find the new weight. The new weight seems to be 3 and not 2.

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Minor improvement in accuracy of loops_per_usec and loops_per_msec calculation

Signed-off-by: Anup Patel <anup@brainfault.org>
[CORE] Allow vmm_vcpu_irq_process() and vmm_vcpu_irq_assert() only for interruptible VCPU states

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Introduce dynamically assigned contextid for L1 tables

This patch introduces dynamically assigned (or on-the-fly incremented) contextid for level1 tables.

Every newly created level1 table will be assigned a new contextid. The lower 8-bits of this contextid will be used as ASID when switching translation tables.

We also revert the "[ARM] arm32: Fix hard-coded weight in arch_delay_loop_cycles()" change because this patch makes it redundant on Beagleboard-xM and Hackberry.

Signed-off-by: Anup Patel <anup@brainfault.org>