mmc: msm_sdcc: set IO_PAD_PWR_SWITCH bit based on IO voltage level

SDCC4 controller has IO_PAD_PWR_SWITCH control bit in MCI_CLK register.
Driver should set this bit to 1 if the IO voltage level is within
low voltage range (1.7v - 1.9v) else clear it.

But driver sets this bit to 1 only if the MMC core layer initiates
the voltage switch sequence. So if voltage switch sequence is not
initiated (which is the case with non UHS-I cards) then even if
the IO voltage level is within low voltage range, IO_PAD_PWR_SWITCH
bit remains cleared.

This change checks the IO voltage level and based on that sets the
IO_PAD_PWR_SWITCH bit.

CRs-Fixed: 386445
Change-Id: Id0648b0f87ea9bcc942e855e30da810e0fe5ebf5
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
	drivers/mmc/host/msm_sdcc.h
mmc: msm_sdcc: add support for AUTO_CMD19 control

SDR104 (supported by SD3.0 spec compliant SD cards) bus speed mode
requires DLL (Delay Locked Loop for sampling clock generation) HW
block to be tuned if clock rate is >100MHz. To help the sampling clock
tuning SD3.0 specification has added CMD19.

During card initialization, driver uses these tuning commands to search
for optimal sampling point and then programs the DLL HW with this optimal
sampling point.

In addition, our SDCC controller's DLL HW has a mechansim of data
tracking (CDR) which can be enabled during read transaction so the host
will not lose the sampling point as a result of voltage and, especially,
temperature variations. Tuning pattern commands (CMD19) can be sent
automatically by HW (by using AUTO_CMD19 bit) before any RX transaction
for helping the CDR to track after the correct sampling point.

Although sending CMD19 automatically before every read commands is
overhead and reduces read performance by ~1 MB/s. SD spec does
not mandate to send these commands before every read operations.

This change keeps AUTO_CMD19 disabled by default but provides sysfs
attribute to enable or disable AUTO_CMD19 as per need.

Change-Id: I9ef99a8dde9b9733ea99639cdab2b6714ac50d76
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
	drivers/mmc/host/msm_sdcc.h
mmc: msm_sdcc: correct the hardware version number

SDCC core version number in MSM8974 is 0x2b and not 0x2d. Fixing this
and enabling hard reset supported in this newer sdcc core.

Change-Id: Ib216330af59f854ca7ebc8735b624f3005e1ba39
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.h
mmc: msm_sdcc: add support for AUTO_CMD21

Using HS200 (supported by eMMC 4.5 spec compliant cards) bus speed
mode requires DLL (Delay Locked Loop for sampling clock generation) HW
block to be tuned if clock rate is >100MHz so that both host and card
are in sync. eMMC 4.5 spec has added CMD21 for this tuning mechanism.

During card initialization, driver uses the tuning command to search
for an optimal sampling point and then programs the DLL HW with this
optimal sampling point.

In addition, msm SDCC controller's DLL HW has a mechansim for data
tracking (CDR) which can be enabled during read transactions so the host
will not lose the sampling point as a result of voltage and, especially,
temperature variations. Tuning pattern command (CMD21) can be sent
automatically by HW (by using AUTO_CMD21 bit) before any RX transaction
to help CDR keep track of the correct sampling point.

Since sending CMD21 automatically before every read commands is an
overhead, reducing read performance by ~1 MB/s and eMMC spec does not
mandate sending the tuning command before every read operation, this
change adds support for AUTO_CMD21 (and keeps it disabled by default)
while providing a sysfs attribute to enable or disable AUTO_CMD21 as
needed.

Change-Id: I6e053db8878b273a407fa7caf8332eb064f351ce
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
	drivers/mmc/host/msm_sdcc.h
mmc: msm_sdcc: Print data line status in case of errors

The MCI_TEST_INPUT register of the SDC controller depicts the status
of the data lines (if pulled down or not). Print its state in cases of
errors to isolate any device specific issues.

CRs-Fixed: 392889
Change-Id: I5d0dbcf3fb606e6a31ede58d7cc6b27f3fb80af7
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
mmc: msm_sdcc: data timeout errors are expected during HS200 tuning

HS200 bus speed mode requires DLL (Delay locked loop) HW block to be
tuned as clock rate (192 MHz) is greater than 100MHz.

While tuning the DLL block by sending CMD21 for different DLL phases,
it is quite possible that few CMD21 may fail with data CRC/timeout
errors as clock phase is not correct but these errors are not really
worth to be printed out as kernel messages. This change doesn't allow
these errors to be printed.

CRs-Fixed: 401743
Change-Id: I2b465a8e1d52458e8663d48791083be7fa4131b2
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
mmc: msm_sdcc: set DDR timing mode before setting the clock rate

Setting DDR timing mode in controller before setting the clock
rate will make sure that card don't see the double clock rate
even for very small amount duration. Some eMMC cards seems to lock
up if they see clock frequency > 52MHz.

Change-Id: I8105cf52c07df01d66c3e15304ea10e2cbc498ff
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
mmc: msm_sdcc: Reset SPS BAM on error recovery

In the current soft reset sequence performed as part of
CMD/DATA error recovery we do the following:
1) Write 1 to DML_SW_RESET
2) Reset CPSM/DPSM by clearing MCI_CMD and MCI_DATA_CTL
or by writing to MCI_SW_RST_CONFIG.
3) Re-init DML
4) Reconfigure both consumer and producer BAM pipes.

The BAM pipe reset does not reset the sideband signals, since
only SDCC side is reset SDCC - BAM communication will go out
of sync and cause DML to be stuck without transferring data.
Hence reset BAM core every time SDCC is reset (which is on
error recovery).

Fix error handling for sps pipe or device reset.

Change-Id: I745e015c862fffa36a814cd007d2e82383668b3a
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

Conflicts:
	drivers/mmc/host/msm_sdcc.c
slub: fix a possible memory leak

Memory allocated by kstrdup should be freed,
when kmalloc(kmem_size, GFP_KERNEL) is failed.

Acked-by: Christoph Lameter <cl@linux.com>
Acked-by: David Rientjes <rientjes@google.com>
Signed-off-by: Joonsoo Kim <js1304@gmail.com>
Signed-off-by: Pekka Enberg <penberg@kernel.org>
msm: display: Increase timeout value for fence waiting

In some benchmark use case, graphic engine is extremely
busy, need increase the fence waiting timeout value.

Signed-off-by: Ken Zhang <kenz@codeaurora.org>

Conflicts:
	drivers/video/msm/msm_fb.c
msm: display: check get_unused_fd_flags return val

Not checking the error code, which might be negative, will cause us to wrongly
reference fdt[fd] by using the error code, causing kernel panic in fd_install.

Change-Id: I1f8e68e74bdbdd5b81bc3450f7d93b5cd96c9439
Signed-off-by: Iliyan Malchev <malchev@google.com>

Conflicts:
	drivers/video/msm/msm_fb.c