R600: prettier dump of clamp
R600: Factorize Fetch size limit inside AMDGPUSubTarget
R600: Some factorization
R600: Rename 128 bit registers.

Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.
R600: Improve texture handling
R600: Relax some vector constraints on Dot4.

Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
R600: Replace big texture opcode switch in scheduler by usesTC/usesVC
R600: Use depth first scheduling algorithm

It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)
R600: Use bottom up scheduling algorithm
R600: Lower int_load_input to copyFromReg instead of Register node

It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.
Add missing verb to comment in PassNameParser.h
Patch by Mark Seaborn.