creating a gate no longer strips leading zeros
Made evaluator able to eval inverts
Now parses INV as inverts
Small changes to Gate
Added SystemInfo class
Removed sorted option
Almost works
Minor changes to Gate and changes to accomodate for this
Added Comparators
Added Enum
Maybe works
Renamed enum
Added new wireCounter for list of lists
Added some more strict checks to make verify input circuit
Added comment
Added a SPACL parser and updated Driver code
SPACL converter now in converters
Works! But not minimizing AND layers yet
Only do the layer sorting for xor and inv gates

Effectively minimizes the number of ands
Renamed class and fixed output