dcache: avoid read on write to same address

Instead of enabling the RAM bypasses when a read on write happens,
avoid the situation.
This will insert a 1 clock cycle extra latency on refill hits
and write to read accesses, but that can be considered a
good trade-off considering the bypasses are resource thirsty.
icache: avoid read on write to same address

Instead of enabling the RAM bypasses when a read on write happens,
avoid the situation.
This will insert a 1 clock cycle extra latency on refill hits,
but that can be considered a good trade-off considering
the bypasses are resource thirsty.