Misc Cortex-A5 changes include new file for cache operations
A few more Cortex-A5 and SAMA5 files
Add some preliminary linker scripts in order to begin building the SAMA5 target
Add system timer logic for the SAMA5
SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable.  Add skeleton file for SAMA5 interrupt management.  Also change from last commit that was left in the editor
SAMA5 interrupt handling logic
Add SAMA5 clock logic.  Cloned from SAM3U and not yet verified
SAMA5 clock configuration should now agree with Atmel sample code; Added header file with macros to enable and disable peripheral clocking
Add support SAMA5 UART and serial driver
Add SAMA5 GPIO configuration support
Add SAMA5D3 pin multiplexing definitions
SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
ARMv7-A:  Need 8-byte stack alignment when callign C code from interrupt handlers.  This change needs to be ported to other ARM architectures as well
Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A
ARMv7-N: Fix a copy error introduced in the previous check-in
Improve Cortex-A5 context switching so that a little less copying is done
Revamp the way external memory regions are configured; Add logic to add SAMA5 external memory regions to the heap
Update SAMA5D3x-EK board configuration to support on-board UART connections, LEDs, and push buttons
Fix SAMA5 vector linking issue
Fix an uninitialized register error that crept into the ARM9 start up code many years ago and was recently cloned into the Cortex-A5.  Obviously no on has used NuttX with ARM9 for years