[FIX] Write data failure on control status register & byte/Word operations on Memory is fixed

-- Removed the chipsel from write data valid, since there is a chance to change address if AWVALID is generated correctly
-- Possibility of changing STROBE signal before completing the operation because of wrong mux sel changed to state depend.
-- Cleanups on codes
[FIX] Parallel Interface INOUT pins condition modified
 --  INOUT pins need active low trigger to make data out, modified INOUT pins for that in axi_hostinterface.vhd
 --  Few cleanups in codes
[FIX] Modelsim simulation error is fixed
--compilation files pointed to wrong filename is fixed
FIX] Fix for Byte/Word write operations over writing nearby bytes
-- Read the data from the address before replacing the byte/word data in the memory location
* [NEW FEATURE] Test environment for Parallel Interface for Host interface IP added
-- Added Parallel Master for enabling parallel operations with the help of bus master
-- Prepared verification environment for Parallel interface verification In host interface IP