First pass at re-factoring into library of parts.

Memory.v broken down into parts. Needs cleanup.
New Octavo/Octavo dir holds CPU implementations. Needs major work.
Scalar almost OK as-is, SIMD needs overhaul to remove layering.
moved back to rden to minimize changes across system while rebuilding. Will change that later.
Scalar Octavo now rebuilt and working as before.

Stub top-level wrapper in Generator.
Initial refactored SIMD. Needs work:

test bench not working
partition templates need re-doing (temp. set to False in parameters)
SIMD now debugged and tested for synthesis and simulation.
partition generation fixed. Defaults to True. Layering removed.
Started IO predication. Moving stuff out of Memory in to Misc and IO, and generalizing.
Started IO predication. Moving stuff out of Memory and generalizing. (part 2)
Abstracted rden/wren generation. About to start implementing I/O subsystem.
Begun work on IO module. First stage done.
IO module parts almost done.
IO module parts almost done.
Merge branch 'Predication' of https://github.com/laforest/Octavo into Predication
More IO work. Realized I forgot different threads test the write port and do a write.
Factoring IO into IO_Read and IO_Write modules.

These modules will have to interconnect for IO_Ready check,
and the overall IO_Ready signal now will be generated externally to
the IO modules.
First pass at generic IO Read module. Not tested/debugged AT ALL.
typo fix while reviewing design
Factored out common idioms.

Now both IO_Read and IO_Write will sport common IO_Check modules.
All IO Ready detection simplified.
IO_Read and IO_Write first pass. Untested.
Translator needs no clock, and added external write enable to IO_Write.