Miscellaneous pin-swapping for signals to the microcontroller.
Moved uC <-> FPGA SPI interface to FPGA bank 5.
Relocated I2C pins on FPGA to route to DDR2 socket, to uncrowd the routing region between banks 5 and 6.
Added inverter to enforce exclusive behavior of front end VRAW_SW and VCCIO default voltage.
Routing is complete, though I haven't decided what to do about the USB SS ID pin, and where to plop the direct access to FPGA JTAG signals.
Added LED indicators (3.3V digital power, microcontroller GPIO).
Added GPIO push button, sharing signal with DDR2 SA1.
Change 2x5 SWD/JTAG connector to surface mount.