Using xml to keep the hierarchy
I can add port and their direction to xml.
good. We can parse the vhdl and create a hierarchy now.
vhdl.py is our entry point now.
we can figure out the hierarchy now.
This generates the hier.xml. We should attach it to design.xml
We can compile. Elaborate tomorrow.
We can elaborate now.
Fixed a bug. Now a topentity is elaborated rather than the last entity.
To Do : We need to generate the test bench now.
removed unneeded functions.
Generate testbench and we are good to go.
This generates a testbench. We should save it.
Go have your tea and finish this algorithm.
Sets are produced and we should analyze them now to produce the hierarchy
Generated the hierarchy in xml. test on hpc13
Component instantiation can also have generic map along with port maps.
Merge branch 'master' into ncurses