[ARCH] ARM - GIC - Register definitions must be volatile for optimised builds to function.
[DRIVERS] SDCard - Always use multiple block read/write command. Added some transfer in progress state recovery.
[MACH] Zynq - Ensure SLCR register I/O definitions work on optimised builds.
[DRIVERS] SDHCI - Improvements to SD Host Controller Interface driver.

* Some basic reset on error state.
* BT_ThreadYield on polling.
[MACH] ZYNQ - Uart driver error code correction.
[MACH] ZYNQ - Devcfg Interface - Initial implementation.
[MACH] ZYNQ - Corrected SLCR register definitions.
[MACH] ZYNQ - Use of SLCR registers is volatile.
[MACH] ZYNQ - Added Device configuration driver Devcfg for loading FPGA's via the PCAP interface.
[ARCH] ARM - default int handler bugfix
[HAL] LPC11xx - Added support for FIFO
[LIB] FIFO - bugfix in FIFORead
[HAL] LPC11xx - added id parameter to identify timer
[OS] CAN - support for buffered and polled mode
[ARCH] ARM - split to different chip derivates
[ARCH] ARM - support for GPIO configuration at startup
[OS] bugfix UART initialization
[BSP] LPC11xx - Modified KConfig
[HAL] LPC17xx - first implementation of LPC17xx platform
[FIX] bt_main() should always use a boot uart in polled mode.