hdl/modules/wb_position_calc/*: add reset 2x port

Added reset synchronous to fs_clk2x domain. Now, each clock
domain has its own synchronous reset port
hdl/modules/dsp_cores_pkg.vhd: update entities definitions

Added reset_2x ports for wb_position_calc_core.vhd
and xwb_position_calc_core.vhd