Minor altera build improvements, and new support for devices in containers
core/container/hdl/src/HdlContainer.cxx: enable active flow control for fpga->fpga flow (has issues).
components/file_write.rcc/file_write.c: extra error check when output is named pipe
core/local/util/ezxml/include/OcpiUtilEzxml.h: make "element" arg to getRequiredString optional
core/local/util/ezxml/src/OcpiUtilEzxml.cxx: ditto
core/local/util/misc/include/OcpiUtilMisc.h: add more compare and hash functions
-- prepared for using unordered STL collections
hdl/devices/dac.hdl/Makefile: remove old Makefile junk/libraries
hdl/devices/dac.hdl/dac.v: fix wti inputs (not really used anyway)
hdl/devices/dac.hdl/dac.xml: widen wti to 64 bits to be consistent with verilog
hdl/primitives/bsv/bsv_pkg.vhd: add SyncFIFO VHDL component to instance it from vhdl
hdl/primitives/ocpi/Makefile: add dependency: this lib depends on the bsv lib
tools/cdk/include/hdl/altera.mk: more/better logging, timing and error output
tools/cdk/include/hdl/quartus.mk: ditto
tools/cdk/include/hdl/hdl-assembly.mk: allow ".xml" in container names
tools/cdk/include/hdl/hdl-lib2.mk: properly support libraries depending on other libraries finally
tools/cdk/include/hdl/hdl-make.mk: improve time output
tools/cdk/include/hdl/hdl-pre.mk: avoid including default libraries when compiling libraries
tools/cdk/include/util.mk: support debug printing of variables that are callable
tools/ocpigen/include/hdl-platform.h: major update for devices in containers and initial card/slot support
tools/ocpigen/src/hdl-platform.cxx: ditto
tools/ocpigen/include/wip.h: make Signals class a map to allow easy dup checking etc.
tools/ocpigen/src/hdl-assembly.cxx: use new Signals class which is now a map
tools/ocpigen/src/parse.cxx: ditto
tools/ocpigen/src/wip_HDL.cxx: ditto