Remove hard-coded mappings related to Armada XP support

Armada XP initialization flow requires SoC registers to be
mapped very early in order to configure Snoop Filter for SMP.
Additional mapping in locore.S is redundant as proper mapping is
made in pmap_devmap_bootstrap() prior to calling cpu_setup() which
configures the Snoop Filter.
For secondaru CPUs it is better to pass VA of the SoC
registers defined in MV_BASE and PA consistent with the value
in the Device Tree.

Tested by:	kevlo
Fix-up DTB for Armada XP registers' base according to the actual settings

Depending on u-boot's flavor some boards have their SoC registers
base address configured to 0xD0000000 and other to 0xF1000000.
U-boot is passing currently set value via CP15 register.
In order to create proper mapping for SoC registers and allow further
successful initialization it is necessary to replace fdt_immr_pa with
the real value and eventually fix-up device tree blob.

Tested by:	kevlo
Change Armada XP kernel load address to the u-boot's end address

Loading kernel to 0xf00000 has no practical reason.
Starting it from the u-boot's highest possible end address
(2MB counting from 0x0) makes more sense.

Tested by:	kevlo
Remove not working and deprecated PJ4Bv6 support

Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

Since CPU_MV_PJ4B describes ARMv7 compliant CPU there is no need for
sending an IPI each time when TLB is flushed in any way.

Tested by:	kevlo