clocksource: sun4i: change CPU mask to cpu_possible_mask

The interrupt for the timer is a shared interrupt, so any CPU can handle
it. Switch to cpu_possible_mask.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clocksource: sun4i: Increase a bit the clock event and sources rating

We want to keep this driver as the default provider of the clock events
and source, yet some other driver might fit in the "desired" category of
ratings. Hence, we need to increase a bit the rating so that we can have
more flexibility in the ratings we choose.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
clocksource: Add Allwinner SoCs HS timers driver

Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.

The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun5i: a10s: Add support for the High Speed Timers

The Allwinner A10s has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun5i: a13: Add support for the High Speed Timers

The Allwinner A13 has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
ARM: sun7i: a20: Add support for the High Speed Timers

The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.

Now that we have a driver to support it, we can enable them in the
device tree.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
reset: Add Allwinner A31 Reset Controller Driver

The Allwinner A31 has an IP maintaining a few other IPs in the SoC in
reset by default. Among these IPs are the High Speed Timers, hence why
we can't use the regular driver construct, and need to call the
registering function directly during machine initialisation.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER

The A31 has a reset controller, and we have to select this option to
have access to the reset controller framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sunxi: Register the A31 reset IP in init_time

The A31 has a reset IP that maintains a few other IPs in reset by
default. Among these IPs are the UARTs, and most notably the timers. We
thus need to register the reset driver before initializing the timers so
that the reset timer can use the reset framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: sun6i: Add the reset controller to the DTSI

The A31 has a reset controller IP that maintains a few other IPs in
reset, among which we can find the UARTs, high speed timers or the I2C.
Now that we have support for them, add the reset controllers to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
reset: Fix mpripard's reset patch
ARM: sun4i: dt: Add bindings for USB clocks
clk: sunxi: Add support for USB clocks
ARM: sun4i: dt: Add USB EHCI bindings
ARM: sunxi: usb: Add Allwinner sunXi EHCI driver
ARM: sun4i: dt: Add EHCI bindings to the Mele A1000
ARM: sun4i: dt: Add EHCI bindings to Cubieboard-A10
ARM: sun7i: dt: Add bindings for USB clocks
ARM: sun7i: dt: Add USB EHCI bindings
ARM: sun7i: dt: Add USB EHCI bindings for Cubieboard2