cfg80211: Fix memory leak

When a driver requests a specific regulatory domain after cfg80211 already
has one, a struct ieee80211_regdomain is leaked.

Change-Id: Id28fc9861b9c911a97bd242439eabca097d76258
Reported-by: Larry Finger <Larry.Finger@lwfinger.net>
Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: b7566fc363e23f0efd3fa1e1460f9421cdc0d77e
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[mattw@codeaurora.org: trivially backport to the msm-3.4 kernel]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: vidc: Initialize kernel space stack variables

This change initializes kernel space stack variables
that are passed between kernel space and user space
using ioctls.
Non initialization of these variables may lead to
leakage of memory values from the kernel stack to
user space.

PS2-3: Correct authorship and date.

Change-Id: I5b45f3a7baf9c538fee2ec356cd8545f8b042b5e
CRs-fixed: 556771,563420
Signed-off-by: Deepak Verma <dverma@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Linux 3.4.0 -> 3.4.71

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Revert "msm: kgsl: Add an input handler to power up the GPU on a touch event"

This reverts commit 380f174ac7b5fadba93fdd5b8456596bf0cf532b.
Revert "msm: kgsl: Allow GPU start to run in a high priority queue"

This reverts commit a96d2876909b2e0575ccedc1866970d8bc45bca7.
msm: krait-regulator: fix up CPU_UP_CANCELED handling

The driver handles CPU_UP_CANCELED as if the core went ONLINE. This
leads to smp call functions on that cpu even when the cpu is offline.
Make CPU_UP_CANCELED force bhs on the target cpu, since it is still
offline.

Change-Id: I668dbfd947d836a1f468d57372e73fbd08dd437e
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: clock: Don't update clk->parent in clk_set_parent()

Any change to the parent field has to be done between __clk_pre_reparent()
and __clk_post_reparent() to avoid race conditions. So, stop setting the
parent field and leave it to the ops->set_parent() implementations to
update the parent field. All current implementations of ops->set_parent()
already do so.

Change-Id: Idc41bee306881a885335ecb322a21509231048cc
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: clock: Check that round_rate is less than fmax

HW has maximum frequency requirements. Ensure that the clock frequency
returned from clk_round_rate() is within these limits.

Change-Id: I0d4ed5851fc1f9f76c0ad0622cc6609e64e5311f
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations

Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.

For instance in the following function:

void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
	memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
	waiter->magic = waiter;
	INIT_LIST_HEAD(&waiter->list);
}

compiled as:

800554d0 <debug_mutex_lock_common>:
800554d0:       e92d4008        push    {r3, lr}
800554d4:       e1a00001        mov     r0, r1
800554d8:       e3a02010        mov     r2, #16 ; 0x10
800554dc:       e3a01011        mov     r1, #17 ; 0x11
800554e0:       eb04426e        bl      80165ea0 <memset>
800554e4:       e1a03000        mov     r3, r0
800554e8:       e583000c        str     r0, [r3, #12]
800554ec:       e5830000        str     r0, [r3]
800554f0:       e5830004        str     r0, [r3, #4]
800554f4:       e8bd8008        pop     {r3, pc}

GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.

This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:

Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).

Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:

save r8:
-       str     lr, [sp, #-4]!
+       stmfd   sp!, {r8, lr}

and restore r8 on both exit paths:
-       ldmeqfd sp!, {pc}               @ Now <64 bytes to go.
+       ldmeqfd sp!, {r8, pc}           @ Now <64 bytes to go.
(...)
        tst     r2, #16
        stmneia ip!, {r1, r3, r8, lr}
-       ldr     lr, [sp], #4
+       ldmfd   sp!, {r8, lr}

Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:

save r8:
-       stmfd   sp!, {r4-r7, lr}
+       stmfd   sp!, {r4-r8, lr}

and restore r8 on both exit paths:
        bgt     3b
-       ldmeqfd sp!, {r4-r7, pc}
+       ldmeqfd sp!, {r4-r8, pc}
(...)
        tst     r2, #16
        stmneia ip!, {r4-r7}
-       ldmfd   sp!, {r4-r7, lr}
+       ldmfd   sp!, {r4-r8, lr}

Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".

Change-Id: I79a0d6897572b693d50f8ea8a94aa331bfcc59f8
Git-Commit: 455bd4c430b0c0a361f38e8658a0d6cb469942b5
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7670/1: fix the memset fix

Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value.  However the memset itself became broken
by that patch for misaligned pointers.

This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.

Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.

While at it, the entry instructions are slightly reworked to help dual
issue pipelines.

Change-Id: I5db45a7de1e389bacb5d6e4513c0d446ae2c9440
Git-Commit: 418df63adac56841ef6b0f1fcf435bc64d4ed177
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
USB: gadget: rndis: Optimize tx path for better performance

Current rndis header addition and aggregation steps:
1. Increase skb headroom by size of rndis header.
2. Copy skb data with newly created skb having more headroom.
3. Create and add rndis header with it.
4. Again copy skb data with usb request buffer for aggregation purpose.

New optimized steps :
1. Create and copy rndis header directly with usb request buffer
2. Copy skb data with usb request buffer

Above new steps avoids cpu intensive skb operations which reduces CPU
usage and provide better throughput.

This change also assigns completion handle with usb request at the time
of usb request creation instead of assigning everytime before queueing
usb request.

CRs-Fixed: 551363
Change-Id: Ifc64d6a8573f6a24e28c73ef9a19b62649e171cd
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: camera2: cpp: Reduce debug prints in cpp driver

The cpp driver had prints to monitor the status when node
is closed. This change makes them as pr_debug messages.

Change-Id: I8a78e6b38d7a702ed38f980d8fa658f50439da0f
Signed-off-by: Rajakumar Govindaram <rajakuma@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Merge remote-tracking branch 'franco/android-msm-hammerhead-3.4-kk-r1' into android-msm-hammerhead-3.4-kk-r1