Re-add voltage dependencies for MPU->CORE and IVA->CORE
previous removal caused screen flickering sometimes. Thanks to anarkia1976 for pointing this out.
OMAPDSS: drop small YUV encoded frames on OMAP44xx

OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.

Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Revert "mm/page_alloc.c: min_free_kbytes to 8192"

This reverts commit 2cd10e854465ee20ee95fddede69467c3ee85f7b.
ARM: OMAP4460: Fixed missing dependency map of OPP for iva

Added missing dependency map of OPP-Nitro and OPP-SpeedBin for iva.
Without this line setting IVA into high OPP fail with errors:

rpres iva.0: _dep_scan_table: 1375000 volt map missing in vdd_core
rpres iva.0: omap_device_scale: Error in scan domains for vdd_iva

Change-Id: I73df4897e886a2d4c9fa22abcbc8a6f34c2a8503
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
OMAP4460: add Reverse Body-Bias support to ABB LDO

On 4460 all OPPs have pre-determined states for VDD_MPU's ABB LDO,
except for OPP_TURBO.  OPP_TURBO may require bypass, FBB or RBB
depending on a combination of characterisation data blown into eFuse
register CONTROL_STD_FUSE_OPP_DPLL_1.

Bits 18 & 19 of that register signify DPLL_MPU trim (see
arch/arm/mach-omap2/omap4-trim-quirks.c).  OPP_TURBO might put MPU's ABB
LDO into bypass or FBB based on this value.

Bit 20 siginifies if RBB should be enabled.  If set it will always
override the values from bits 18 & 19.

The table below captures the valid combinations:

Bit 18 | Bit 19 | Bit 20 | ABB type
0        0        0        bypass
0        1        0        bypass  (invalid combo)
1        0        0        FBB     (2.4GHz DPLL_MPU)
1        1        0        FBB     (3GHz DPLL_MPU)
0        0        1        RBB
0        1        1        RBB     (invalid combo)
1        0        1        RBB     (2.4GHz DPLL_MPU)
1        1        1        RBB     (3GHz DPLL_MPU)

This patch introduces ABB type detection into the ABB init code and
makes a few changes to the ABB programming code to allow for RBB (which
was previously unsupported).

This patch also changes OPP_TURBO's default abb_type to FAST_OPP (FBB)
by default.  This tiny optimization benefits production silicon by
removing one PRCM register write from the ABB initialization code for
the common case where the DPLL_MPU trim values are blown in and the
silicon is weak or nominal (uses FBB at OPP_TURBO).

Change-Id: I73973ddbb77dd89a7e2809bc56d935767f20a5d8
Signed-off-by: Mike Turquette <mturquette@ti.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
OMAP4460: OPP: Move ABB update for MPU OPP turbo to OPP init code

Initially ABB type update was implemented in ABB init code.
This leads to a voltage values duplication.
This patch moves ABB type detection into the OPP init code.

Change-Id: I6140dff1be0f2b9e667160da957c8e1dbabf3e8f
[taras@ti.com: remove previous implementation]
Signed-off-by: Taras Kondratiuk <taras@ti.com>
[nm@ti.com: movement of code to central opp update]
Signed-off-by: Nishanth Menon <nm@ti.com>
[mturquette@ti.com: original author]
Signed-off-by: Mike Turquette <mturquette@ti.com>

Conflicts:
	arch/arm/mach-omap2/ldo.c
	arch/arm/mach-omap2/opp4xxx_data.c
opp4xxx_data.c: Adjust L3, FDIF, HSI and DSS voltages to the earlier introduced OMAP4460_VDD_CORE_OPP75_UV
Fancy Kernel r17