spi: fsl_espi: Use DIV_ROUND_UP instead of open-coded

Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
spi: mpc8xxx_spi: Use DIV_ROUND_UP instead of open-coded

Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
sf: eon|spansion|ramtron: Fix code cleanup

- line over 80 characters
- insert the expression in same line

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: sst: Fix code cleanup

- line over 80 characters
- add spaces
- add tabs

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: stmicro: Fix code cleanup

- line over 80 characters
- foo * bar -> foo *bar
- removed unnecessary for single statement blocks.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Fix code cleanup

- line over 80 characters.
- CHECK: Alignment should match open parenthesis

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
cmd_sf|env_sf: Fix code cleanup

- line over 80 characters
- add tabs
- CHECK: Alignment should match open parenthesis

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Fix code cleanups

- CHECK: Alignment should match open parenthesis
- trailing whitespace

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
cmd_sf: let "sf update" erase last sector as a whole

make "sf update" work with unaligned `len' parameter, by deleting the
whole last sector before writing, so to allow for:

 sf update ${load_addr_r} 0 ${filesize}

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
spi: Add zynq spi controller driver

Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
sf: sst: Add support for SST25WF080

Add support for SST25WF080 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: Enable CONFIG_ZYNQ_SPI

Tested spi on zynq board with sst flash by enabling
CONFIG_ZYNQ_SPI.

sf probe 1:1 0 0
SF: Detected SST25WF080 with page size 4 KiB, total 1 MiB

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
microblaze: Call spi_init function

Initialization spi.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
powerpc/85xx: Add TWR-P10xx board support

TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot

Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/srio: Update the SRIO LIODN registers and ID table macro

For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
powerpc/b4860: Correct LIODN assignment for SRIO

For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
powerpc/t4: Correct LIODN assignment for SRIO

For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file

Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/fm: Fix compiling error if FW location is not defined

FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.

Signed-off-by: York Sun <yorksun@freescale.com>
mpc85xx: Base emulator support

Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>