verif/dc_ram: explicitly initialize memory contents.
rtl: add a simple instruction cache.

This is a direct mapped cache and currently only supports read
operations.  The valid bits are implemented as flops for quick
invalidation and the cache defaults to 8KB in size with a 32 byte line.
rtl/debug: implement cache sync function.

This is used to flush the data cache and invalidate the entire
instruction cache to provide coherency when writing to memory from the
debugger.
rtl/oldland: hook up the instruction cache.
cpu: wire the running bit back up.

This was missed when refactoring the pipeline and core.
tests: add a self-modify instruction cache test.
docs: we now have an instruction cache.