[NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value
[NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
[NVPTX] Add support for native SIGN_EXTEND_INREG where available
[NVPTX] Handle signext/zeroext attributes properly

Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions
[NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
[NVPTX] 64-bit ADDC/ADDE are not legal
[NVPTX] Cut down on physical register defs

We are using virtual registers throughout now, but we still need
to keep a few physical registers per class around to keep the
infrastructure happy.
[NVPTX] We dont use NVBuiltin anymore