Simplify Exec ; scrap `valid` control
Simplification, elaboration, cosmetics
All-negedge operation

Works on hardware, at least intermittently (sometimes freezes after
program, sometimes runs).
Clock up to 20MHz, valid -> locked
Connect halt and reset to dev board pins

T10 = halt  switch = SW0  = halt[4]
C9  = halt  button = BTND = halt[3]
A8  = reset button = BTNU = reset

Reset works repeatably, and halt is effective, but device doesn't come
out of halt once it has gone in.
Recover from halt condition

There was a logic error with the `cyc` shift register that prevent
recovery from halt. Works both in simulation and on hardware now.
Remove incorrect and unnecessary logic

The constraint on i_addr update almost certainly was a race that could
cause jumps not to be taken coming out of halt. The constraint on rhalt
update was redundant with the enclosing `_en` constraint.
Drop core clock to 15MHz

Resolves timing errors (max frequency approximately 15.083MHz according
to ISE). Need to improve timing next, but this appears stable and
functional.