implement binary subtraction in ALU.
implement BCD addition in ALU.
fix missing items in sensitivity list.
work towards using ALU to calculate instruction results.
implement several ALU based instructions.
implement SBC
implement remaining binary ALU operations.
fix bugs in shift operations accumulator mode.
progress towards implementing memory modifying instructions.
complete implementation of ASL memory addressed modes.
initial document describing cycle counts of instructions.
updated docs with cycle time info and revised memory map.
implement LSR.
note incomplete status of BRK.
fix BRK implementation.
remove unused states from CPU FSM.
implement DEC
implement INC
remove redundant null statements from instruction cases.
implement ROL and ROR and make illegal ops do NOP for now.
implement MemoryWrite state for CPU FSM.
remove redundant comment from BRK instruction.
implement instruction pre-fetching when last memory access of
previous instruction does not conflict with instruction fetch.