arm: mvebu: avoid hardcoded virtual address in coherency code

Now that the coherency_get_cpu_count() function no longer requires a
very early mapping of the coherency unit registers, we can avoid the
hardcoded virtual address in coherency.c. However, the coherency
features are still used quite early, so we need to do the of_iomap()
early enough, at the ->init_timer() level, so we have the call of
coherency_init() at this point.

Unfortunately, at ->init_timer() time, it is not possible to register
a bus notifier, so we add a separate coherency_late_init() function
that gets called as as postcore_initcall(), when bus notifiers are
available.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arm: mvebu: remove hardcoded static I/O mapping

Now that we have removed the need of the static I/O mapping for early
initialization reasons, and fixed the registers area length that were
broken, we can get rid of the static I/O mapping. Only the earlyprintk
mapping needs to be set up, using the debug_ll_io_init() helper
function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arm: mvebu: mark functions of armada-370-xp.c as static

All the functions in armada-370-xp.c are called from the
DT_MACHINE_START function pointers, so there is no need for them to be
visible outside of this file, and we therefore mark them as static.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arm: mvebu: switch internal register address at runtime if needed

On Marvell platforms, the "internal registers" is a window of 1 MB of
the physical address space that contains all the registers for the
various peripherals of the SoC (timers, interrupt controllers, GPIO
controllers, Ethernet, etc.). The base address of this 1 MB window is
configurable, and this base address is configured using a register
that is itself part of this window.

All earlier families of Marvell EBU SoCs supported by Linux used
0xf1000000 as the base address of the internal registers window. For
some reason, early versions of the Marvell 370/XP platforms used
0xd0000000 as the base address. This base address is set up by the
bootloader. However, in order to keep as much physical address space
to address RAM below the 4 GB limit, we had to switch the base address
of the internal registers window back to 0xf1000000, and we wanted to
achieve that without breaking existing platforms, where the bootloader
was initially setting the base address to 0xd0000000. So the kernel is
responsible for switching to 0xf1000000 when needed.

One particular bit of a CP15 register has been chosen to indicate
whether we use an old bootloader (setting the address at 0xd0000000)
or a new bootloader (setting the address at 0xf1000000). In the
->map_io() function, when the bit is already set, there is nothing to
do, we are already using a new bootloader and internal registers are
at 0xf1000000.

However, when the bit is not set, we do a static mapping of the
register area that allows to change the internal register address, we
change this address, and set this bit.

Note that this mechanism also needs cooperation from the earlyprintk
addruart handler (in arch/arm/include/debug/mvebu.S) and the early
secondary CPU initialization code (in arch/arm/mach-mvebu/headsmp.S).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arm: mvebu: switch to a different CP15 bit

Note: this should be squashed into the previous commit. Normally, the
new CP15 bit used in this commit should be the official one, but for
now it doesn't work: the kernel boot crashes at a random location, in
a behavior that is identical to what happens when earlyprintk for the
secondary CPUs causes a crash. So it seems like secondary CPUs are not
able to set this bit.

To be investigated by Lior.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>