ARC: [plat-eznps] Add eznps platform

This platform include boards:
	Hardware Emulator (HE) version 0,1...
	Simulator based upon nSIM.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps default board configurations

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps DTS file

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add device for Data Plane Linux

Add new device /dev/dpl.
This device enable access to cmem in other cores.

It is usefull for debugging when gdbserver is attached to process
which runs in a different CPU than gdbserver.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Tal Zilcer <talz@ezchip.com>
ARC: [SMP] TLB flush

This is for cases we need to flush tlb's in several CPU's since a memory
structure may be held by several threads in the same time in different
CPU's.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [SMP] ASID handle

Each CPU got its own TLB and therefore it's own software cache.
Each mmu context may reside at the same time in several CPU's
thanks to posix threads sharing the context.
Therefore may have different ASID.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Add initrd from external file.

We now can easly get rootfs from external file.
It may be cpio, ext2, cramfs...

This makes vmlinux usable not only for internal cpio.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Handle un-aligned user space access in BE.

Adding endian awarness to un-aligned access exception handling.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add CPUSET/NOHZ syscall hooks

CPUSET/NOHZ requires hook for each entry and exit from kernel
of dyntick enabled task.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add CPUSET/NOHZ fault/trap handling hooks

CPUSET/NOHZ requires hooks for entry and exit from/to kernel.
This patch adds the needed ARC hooks for traps and faults.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] add support for NO_HZ_FULL

Select configuration needed as NO_HZ_FULL deps.

Signed-off-by: Noam Camus <noamc@ezchip.com>
time: remove 64BIT config dep for NO_HZ_FULL

Although ARC is 32BIT I still wan't to use NO_HZ_FULL.

Signed-off-by: Noam Camus <noamc@ezchip.com>
vmstat: remove vmstat workqueue.

With NO_HZ_FULL the task of vmstattimer is annoying.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add use of schedule_user

only when CONFIG_CONTEXT_TRACKING

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: handle large offstes to st.as

It happens when NR_CPUS is big i.e. 4k

Than the task_struct is getting too big.
It is due to cpumask which become 128 Bytes

So assembly code using st.as fails while compilation.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: SMP failed to boot due to missing IVT setup

Commit 05b016ecf5e7a "ARC: Setup Vector Table Base in early boot" moved
the Interrupt vector Table setup out of arc_init_IRQ() which is called
for all CPUs, to entry point of boot cpu only, breaking booting of others.

Fix by adding the same to entry point of non-boot CPUs too.

read_arc_build_cfg_regs() printing IVT Base Register didn't help the
casue since it prints a synthetic value if zero which is totally bogus,
so fix that to print the exact Register.

[vgupta: Remove the now stale comment from header of arc_init_IRQ and
also added the commentary for halt-on-reset]

Cc: Gilad Ben-Yossef <gilad@benyossef.com>
Cc: Cc: <stable@vger.kernel.org> #3.11
Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ARC: rw lock for eznps

Current implementation suffered from livelock at nSim.

It occurred while writer holds the lock spinlock and to see that
the lock is readers free.
The reader in a try to release the lock spins on the spinlock the writer
took.
In a periodic manner each time writer quanta at nSim is ended it stills
holds the spinlock and therefore reader is not able to release the lock
since spinlock is taken.

eznps ISA provides atomic operations like compare exchange and
conditional decrease as well as atomic increase.
This way no need for the counter protection spinlock and fair well to
the livelock.

Signed-off-by: Noam Camus <noamc@ezchip.com>