arm: zynq: Enable Cortex-A9 Errata

This patch enables the ARM Cortex-A9 errata.  Here are the list of errata:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
               +                  +                                                +
Xilinx Answer  +  ARM Errata No.  +                 Description                    +
Record No.     +                  +                                                +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    47549      +      742231      + System Deadlock can occur in SMP Mode when the +
               +                  + Same Cache Line is Accessed by Both CPUs & ACP +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    47547      +      754322      + Following an ASID Switch, Faulty MMU Transla-  +
               +                  + tions can occur                                +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    47550      +      764369      + Cache Line Maintenance Operations by MVA might +
               +                  + not Succeed on an Inner Shareable Memory Region+
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    -----      +      742230      + DMB operation may be faulty                    +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    -----      +      743622      + Faulty hazard checking in the Store Buffer may +
               +                  + lead to data corruption                        +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    -----      +      754327      + No automatic Store Buffer drain                +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    52031      +      775420      + A data cache maintenance operation which aborts+
               +                  + might lead to deadlock                         +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    -----      +      720789      + TLBIASIDIS and TLBIMVAIS operations can broad  +
               +                  + cast a faulty ASID                             +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    -----      +      751472      + Interrupted ICIALLUIS may prevent completion of+
               +                  + broadcasted operation                          +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>