AVX-512: Add perfomtest-compliant headers to test cases

test/avx512*.asm files are now tested by using perfomtest.pl
Refer to pefomtest help message for the usage.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
parser: simplify code by keeping a pointer to the current operand

There is an awful lot of syntax-heavy "result->oprs[operand]" going
on; simplify by making a pointer to the current operand.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
parse: factor out mref parsing

Factor out the parsing of an mref from parse_line().  In order to
support the [base,index] syntax we need to be able to parse an mref in
two steps.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
parser: support split base,index effective address

Mostly intended for the "mib" expressions in BNDLDX/BNDSTX.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
disasm: add support for emitting split EA format

Add support for emitting split EA format in the disassembler,
indicated by the MIB instruction flag.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX: Add MPX instructions

Added MPX instructions and corresponding parser and encoder.

ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index

As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX: Add BND prefix for branch instructions

BND prefix is used for adding bounds checking protection
across flow control changes such as call, ret, jmp and jcc calls.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX: Add test cases for MPX

MPX test asm files are added. These include all three different styles of
mib syntax (NASM, ICC and gas).

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
SHA: Add SHA instructions

New instruction extensions of SHA family are added.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
SHA: SHA test cases

32bit and 64bit test asm files.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
iflags: Use UINT64_C() for 64bit values

UINT64_C() macro is used for iflags as it becomes 64bit.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX: Adapt GAS's mib syntax with an index reg only

GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
MPX: Move BND prefix indication from bytecode to iflags

As BND prefix validity check conflicts with jcc8 prefix,
IF_BND is added for the instruction templates which can have
bnd prefix for preserving the content of bound register.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
AVX512: Update instruction group

CPUID bit for vptestnm[dq] changed.
vptestnm[dq]: AVX512CD -> AVX512F

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
PREFETCHWT1: Add a new instruction flag

PREFETCHWT1 instruction's CPUID was TBD before.
Now it has its new CPUID bit : PREFETCHWT1

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
AVX-512: Add {evex} instruction prefix

For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Build: Suppress warning messages

Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
match: Improve broadcast opsize matching

Broadcasting operand size is different from the original
operand size because 32b or 64b element is repeated to form a vector.
So when matching a broadcasting operand, opsize should be treated
differently.
The broadcasting element size is specified in the decorator information.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
match: Check the number of elements in broadcasting operands

The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.

For example,
    vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8}   ; good
    vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16}  ; fail qword * 16 = 1024b

    vaddps zmm30,zmm29,DWORD [rcx]{1to16}	 ; good
    vaddps zmm30,zmm29,DWORD [rcx]{1to8}	 ; fail dword * 8 = 256b

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
disasm: style cleanup

Fix indentation.

Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>