ARM NEON: Fix v2f32 float intrinsics

Mark them as expand, they are not legal as our backend does not match them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up code format a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176412 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Creating a vector from a lane of another.

The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.

rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
Mips ISD typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176426 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Clean up datalayout strings so they better match hardware capabilities

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176439 91177308-0d34-0410-b5e6-96231b3b80d8
Bypass Slow Divides

* Only apply divide bypass optimization when not optimizing for size. 
* Fixed bug caused by constant for 0 value of type Int32,
  used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
  64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.

Patch by Tyler Nowicki!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r176381, writing the CHECKs in a more forgiving manner to account for
running llvm-objdump on Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
Mips specific inline assembler constraint 'R'

'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Print move instructions.

"move $4, $5" is printed instead of "or $4, $5, $zero".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumping
GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This
prevents linkonce and linkonce_odr symbols from being DCE'd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176459 91177308-0d34-0410-b5e6-96231b3b80d8
The current X86 NOP padding uses one long NOP followed by the remainder in
one-byte NOPs.  If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact.  From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12.  This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused #includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176467 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.

FIXME: Is it expected for win32 to affect mips targets?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
Print a warning message if compiler-rt can't be built because of old CMake version to make this requirement more visible to users

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176481 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Add support for indirect addressing of non default const buffer

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176484 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Use MUL_IEEE for trig/fdiv intrinsic

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
R600: CONST_ADDRESS node is not marked as mayLoad anymore

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

mayLoad complexify scheduling and does not bring any usefull info
as the location is not writeable at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176486 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Turn BUILD_VECTOR into Reg_Sequence

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8