GRSPW: fixed SET_RMAPEN and SET_RMAPBUFDIS

Both ioctl commands destroyed the control register by writing the
content of the status register into it.
GR1553BC: fix memory leak when closing BC driver
GRPCI: initialize cache-line-size and latency timer

In some GRPCI cores not setting the cache line size could result
in long prefetches on the AMBA bus which would lead to bad
performance when doing PCI reads to GRPCI target interface (DMA).

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
GRETH: updated worker Deamon thread name

The name was probably copied from the DEC21140 driver
GRETH: forcing autonegotiation during PHY initialization

Looking at PHY Ctrl register without reseting it will give back
old register content, that is not stable. Instead the PHY is
reset and the autonogotiation capability is read out and
started if present.
GRETH: changed the PHY initialization sequence

1. read_mii() now returns 0xffff on failure. It is more robust when it
   comes to reading the reset bit in the control register, that is the
   first access.

2. write_mii() now has error printout like read_mii().

3. Additional (optional) PHY access debugging is now available by
   enabling GRETH_DEBUG_MII. Even successful accesses are printed.

4. Let PHY do power-down (not only reset) to get in a good state,
   this is just in case the PHY input pin settings are sampled only
   on PHY power-up on some PHYs.

5. PHY GBit advertisement is disabled if Gbit is not supported by MAC.
   Or forced if supported.

6. Auto-nego is started if supported by PHY, before it was started only
   if default set by PHY.

7. Reset Sequence updated:
     * one must wait until reset bit is self-cleared.
     * the DD (Disable Duplex Detection) bit is set, only affects
       EDCL capable devices. This lets RTEMS handle PHY initialization
GRETH: cleaned up parts of PHY init code
PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performance