Power PC, Approach 1, add Transactional Memory instruction support

The following Transactional Memory instructions are added:
  tbegin., tend., tsr., tcheck., tabortwc.,
  tabortdc., tabortwci., tabortdci., tabort.

The patch implements the first proposal by Julian on how to handle the
TM instructions. The proposal is as follows:

    translate "XBEGIN fail-addr" as "goto fail-addr"; that is: push
    simulated execution directly onto the failure path.  This is simple
    but will have poor performance, if (as is likely) the failure path
    uses normal locking and is not tuned for speed.

The tbegin instruction on Power sets the condition code register to
indicate if the tbegin instruction suceeded or failed.  The compiler
then generates a conditional branch instruction to take the success
or failure code path for the tbegin instruction.  In order to fail the
tbegin instruction, the condition code register is updated to indicate
that the tbegin instruction failed.  This patch assumes that there is
always an error handler for the tbegin instruction.  The other TM
instructions are all treated as no ops as we shouldn't be executing the
sucess transactional code path.

Signed-off-by: Carl Love <cel@us.ibm.com>

Bugzilla 323803

git-svn-id: svn://svn.valgrind.org/vex/trunk@2780 8f6e269a-dfd6-0310-a8e1-e2731360e62c