Fix ShiftShift2Shift 1 ARM-peephole optimizer

The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.

Assembly:
  mov r0, r0, lsr #23
  mov r0, r0, lsr #23

transformed into:
  mov r0, r0, lsr #23

expected was:
  mov r0, #0

The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.

This fixes test/opt/tarmshift.pp

I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@25374 3ad0048d-3df7-0310-abae-a5850022a9f2