hw: Model of Primecell pl35x mem controller

Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory regions. NAND
interfaces are modelled.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

---CHANGELOG---
changed since v3:
Added missing include for assert_no_error()
changed since v2:
Guard against unattached SRAM devices
changed since v1:
use sysbus_mmio_get_region() for SRAM mappings (PMM Review)
fixed header comment s/pl353/pl35x
fixed complie warnings in debug mode (-DPL35X_DEBUG)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
xilinx_zynq: add pl353

Add the pl353 memory controller with both NAND and parallel flashes
attached.

---CHANGELOG---
changed from v2:
removed sysbus_from_qdev usage
fixed include names (rebase)
changed from v1:
fixed property names (see patch 3)
---END---

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>