ARM: OMAP1: fix USB host on 1710

There is a long-standing bug that OHCI USB host controller does
not respond on 1710, because of wrong clock definitions. See e.g.
http://marc.info/?l=linux-omap&m=119634441229321&w=2. All register reads
return just zeroes:

[    1.896606] ohci ohci: OMAP OHCI
[    1.912597] ohci ohci: new USB bus registered, assigned bus number 1
[    1.933776] ohci ohci: irq 38, io mem 0xfffba000
[    2.012573] ohci ohci: init err (00000000 0000)
[    2.030334] ohci ohci: can't start
[    2.046661] ohci ohci: startup error -75
[    2.063201] ohci ohci: USB bus 1 deregistered

After some experiments, it seems that when changing the usb_dc_ck /
SOFT_REQ enable bit from USB_REQ_EN_SHIFT to SOFT_USB_OTG_DPLL_REQ_SHIFT
(like done also on 7XX), the USB appears to work:

[    2.183959] ohci ohci: OMAP OHCI
[    2.198242] ohci ohci: new USB bus registered, assigned bus number 1
[    2.215820] ohci ohci: irq 38, io mem 0xfffba000
[    2.324798] hub 1-0:1.0: USB hub found
[    2.361267] hub 1-0:1.0: 3 ports detected

The patch is tested on Nokia 770.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ARM: OMAP4: clock data: lock USB DPLL on boot

Some versions of the u-boot bootloader do not lock the USB DPLL and
when the USB DPLL is not locked, then it is observed that the L3INIT
power domain does not transition to retention state during kernel
suspend on OMAP4 devices. Fix this by locking the USB DPLL at 960 MHz
on kernel boot.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ARM: OMAP3: hwmod data: keep MIDLEMODE in force-standby for musb

For some unknown reason, allowing hwmod to control MIDLEMODE causes
core_pwrdm to not hit idle states for musb in DM3730 at least.
I've verified that setting any MIDLEMODE value other than "force
standby" before enabling the device causes subsequent suspend
attempts to fail with core_pwrdm not entering idle states, even
if the driver is unloaded and "force standby" is restored before
suspend attempt. To recover from this, soft reset can be used, but
that's not suitable solution for suspend.

Keeping the register set at force standby (reset value) makes it work
and device still functions properly, as musb has driver-controlled
OTG_FORCESTDBY register that controls MSTANDBY signal.
Note that TI PSP kernels also have similar workarounds.

This patch also fixes HWMOD_SWSUP_MSTANDBY documentation to match the
actual flag name.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ARM: OMAP4: PM: fix PM regression introduced by recent clock cleanup

Commit 17b7e7d33530e2bbd3bdc90f4db09b91cfdde2bb ("ARM: OMAP4:
clock/hwmod data: start to remove some IP block control "clocks"")
introduced a regression preventing the L3INIT clockdomain of OMAP4
systems from entering idle.  This in turn prevented these systems from
entering full chip clock-stop.

The regression was caused by the incorrect removal of a so-called
"optional functional clock" from the OMAP4 clock data.  This wasn't
caught for two reasons.  First, I missed the retention entry failure
in the branch test logs:

http://www.pwsan.com/omap/testlogs/cleanup_a_3.9/20130126014242/pm/4460pandaes/4460pandaes_log.txt

Second, the integration data for the OCP2SCP PHY IP block, added by
commit 0c6688753f9912c6a7013549ec31c8844020bbc1 ("ARM: OMAP4: hwmod
data: add remaining USB-related IP blocks"), should have associated this
clock with the IP block, but did not.

Fix by adding back the so-called "optional" functional clock to the
clock data, and by linking that clock to the OCP2SCP PHY IP block
integration hwmod data.

The problem patch was discovered by J, Keerthy <j-keerthy@ti.com>.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
usb: phy: nop: Add some parameters to platform data

Add clk_rate parameter to platform data. If supplied, the
NOP phy driver will program the clock to that rate during probe.

Also add 2 flags, needs_vcc and needs_reset.
If the flag is set and the regulator couldn't be found
then the driver will bail out with -EPROBE_DEFER.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
ARM: OMAP2+: clock data: Remove CK_* flags

The patch removes all the CK_* which were used to identify the family of
processors for which the individual clocks belonged to. Instead now separate
lists are created based on the family of processors.

Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Tested-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register();
 updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ARM: OMAP5: Update SOC id detection code for ES2

Update OMAP5 ES2 idcode and make ES2 as default detection.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: timer: Update the clocksource name as per clock data

OMAP5 clockdata has different sys clock node name. Fix the timer code
to take care of it.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: prm: Allow prm init to succeed

Allow prm init to succeed on OMAP5 SOCs.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: Reuse prm read_inst/write_inst

Make use of 'prm_base' so that  prm read_inst/write_inst can work on
OMAP5 devices.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: Update SAR RAM base address

Update SAR RAM base address for OMAP5 based devices.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: Update SAR memory layout for WakeupGen

On OMAP5 es2 WakeupGen SAR register layout offset have changed.
Update the layout accordingly.

Reported-by: Menon, Nishanth <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: Make errata i688 workaround available

Errata i688 is also applicable for OMAP5 based devices. Update the
code so that it can be enabled on OMAP5 devices.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
ARM: OMAP5: clock: No Freqsel on OMAP5 devices too

OMAP5 does not have freqsel either, so checks needs to be extended.

Infact only OMAP343X devices has the freqsel support, so fix the check
accordingly so that future patching can be avoided.

Reported-by: Archit Taneja <archit@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Merge tag 'omap-fixes-a-for-3.9-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9-rc3/fixes

Miscellaneous OMAP fixes for v3.9-rc.  These primarily deal with OMAP2+ power
management regressions.  There's also a fix for the OMAP1 OHCI controller.

Basic build, boot, and PM test logs are at:

    http://www.pwsan.com/omap/testlogs/fixes_a_3.9-rc/20130314101856/
ARM: OMAP: fix typo "CONFIG_SMC91x_MODULE"

There's a (rather subtle) typo in "CONFIG_SMC91x_MODULE". Fix it once
and for all by using IS_ENABLED(), which is designed to avoid issues
like this.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP1: Remove unused DMA channel definitions

Many of these channel definitions have became unused or were never used
so remove unused definitions from arch/arm/mach-omap1/dma.h using a script
below. See also notes in commit 8c4cc00
("ARM: OMAP1: DMA: Moving OMAP1 DMA channel definitions to mach-omap1")
for removing remaining ones.

egrep '#define OMAP.*DMA' arch/arm/mach-omap1/dma.h \
        |cut -f 1 |cut -d ' ' -f 2 | while read -r i; do \
                if [ `git grep -c $i | wc -l` -eq 1 ]; then \
                        echo "removing" $i; \
                        sed -i "/${i}/d" arch/arm/mach-omap1/dma.h; \
                fi; \
        done

Signed-off-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP2+: Remove unused DMA channel definitions

Many of these channel definitions have became unused or were never used
so remove unused definitions from arch/arm/mach-omap2/dma.h using a script
below. See also notes in commit d5e7c86
("ARM: OMAP2+: DMA: Moving OMAP2+ DMA channel definitions to mach-omap2")
for removing remaining ones.

egrep '#define OMAP.*DMA' arch/arm/mach-omap2/dma.h \
	|cut -f 1 |cut -d ' ' -f 2 | while read -r i; do \
		if [ `git grep -c $i | wc -l` -eq 1 ]; then \
			echo "removing" $i; \
			sed -i "/${i}/d" arch/arm/mach-omap2/dma.h; \
		fi; \
	done

Signed-off-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized

clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.

There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.

Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.

[    0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[    0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0    Not tainted  (3.9.0-rc1-12179-g72d48f9 #6)
[    0.000000] PC is at __kmalloc+0x1d4/0x248
[    0.000000] LR is at __clk_init+0x2e0/0x364
[    0.000000] pc : [<c01174f8>]    lr : [<c0441f54>]    psr: 600001d3
[    0.000000] sp : c076ff28  ip : c065cefc  fp : c0441f54
[    0.000000] r10: 0000001c  r9 : 000080d0  r8 : c076ffd4
[    0.000000] r7 : c074b578  r6 : c0794d88  r5 : 00000040  r4 : 00000000
[    0.000000] r3 : 00000000  r2 : c07cac70  r1 : 000080d0  r0 : 0000001c
[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
[    0.000000] Control: 10c53c7d  Table: 8000404a  DAC: 00000017
[    0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[    0.000000] Stack: (0xc076ff28 to 0xc0770000)
[    0.000000] ff20:                   22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[    0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[    0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[    0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[    0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[    0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[    0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[    0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[    0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[    0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[    0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[    0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[    0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!

It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.

More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html

With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.

This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.

The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.

Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org  # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
Merge tag 'omap-cleanup-a-for-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.10/cleanup

In the OMAP2+ clock data, replace the flags that determine whether a
clock should be registered on a given SoC with per-SoC lists.

Basic build, boot, and power management test results are available at:

http://www.pwsan.com/omap/testlogs/jk_clock_flags_cleanup_3.10/20130318100504/