Move file to X86 and add a triple to fix darwin bots for now.

The problem is due to the section name being explicitly mentioned in
the IR and differing between the two platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187394 91177308-0d34-0410-b5e6-96231b3b80d8
[DAGCombiner] insert_vector_elt: Avoid building a vector twice.

This patch prevents the following combine when the input vector is used more
than once.
insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx
=>
build_vector elt0, ..., NewEltIdx, ..., eltN 

The reasons are:
- Building a vector may be expensive, so try to reuse the existing part of a
  vector instead of creating a new one (think big vectors).
- elt0 to eltN now have two users instead of one. This may prevent some other
  optimizations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187396 91177308-0d34-0410-b5e6-96231b3b80d8
[R600] Replicate old DAGCombiner behavior in target specific DAG combine.

build_vector is lowered to REG_SEQUENCE, which is something the register
allocator does a good job at optimizing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187397 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.

This is the first of many upcoming patches for PowerPC fast
instruction selection support.  This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass.  It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch.  There will
be quite a few tests coming with future patches.

This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only.  It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation.  This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.

This patch has been tested by building and running the
projects/test-suite code with -O0.  All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399 91177308-0d34-0410-b5e6-96231b3b80d8
[Sparc] Use call's debugloc for the unimp instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402 91177308-0d34-0410-b5e6-96231b3b80d8
Remove more dead documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187403 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] check bitwidth in PerformORCombine

When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.

Split the check of the value of the second operands to the ands.  Move the cast
and variable declaration slightly higher to make it slightly easier to follow.

Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
Fix underscore to be the proper length.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187406 91177308-0d34-0410-b5e6-96231b3b80d8
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8