ARM: Remove NSACR from the common code

NSACR (Non-Secure Access Control Register) is AArch32 specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page format

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
EmbeddedPkg/MmcDxe: Update Mmc code to conform to coding standard

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14524 6f19259b-4bc3-4df7-8a09-765794883524
EmbeddedPkg/MmcDxe: Removed redundant CMD12 calls from MMC

Command 12 - Stop transmission (ends read or write).
Normally only needed for streaming transfers or after error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14525 6f19259b-4bc3-4df7-8a09-765794883524
ArmPlatformPkg/PL180MciDxe: Increased the TPL at the highest priority to disable interrupts

This change prevent any interrupt to disturb the PL180 data transfer.
If the data transfer is not fast enough, we get UNDERRUN error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14526 6f19259b-4bc3-4df7-8a09-765794883524