target-arm: A64: add support for add and addi

This patch combines two of the original series for generic add
implementation support. It includes some additional helper functions
that will be useful elsewhere:

  * ext_and_shift_reg for register extension (with opt shift)
  * read_cpu_reg_sp (sp version of read_cpu_reg)
  * gen_set_ZN/ZN64 for setting Z and N flags
  * gen_add/sub_CC for generic arithmetic with flag setting

from Alexander Graf <agraf@suse.de> aarch64 series 15/60 (- extended)
from Alexander Graf <agraf@suse.de> aarch64 series 27/60
from Alexander Graf <agraf@suse.de> aarch64 series 60/60

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

v3 -> v4 (ajb):
      - removed the flag handling helpers, stubbed out TCG equivalent
      - streamlined the generation to avoid duplication

v4 -> v5 (ajb):
      - used Claudio's common add_with_carry for flag ops
      - common as much as possible between addi/add
      - removed extraneous diagrams
      - documented the add (extended register) stub

v5 -> v6 (ajb):
      - drop add_with_carry for now

v6 -> v7 (ajb):
      - fixed dodgy tcg generation.

v7 -> v8 (ajb):
      - fixed merge conflicts with cpu_reg_sp()
      - used Claudio's generic flag helpers
      - add ext_and_shift_reg helper for extension
      - rename disas->handle for actual implementations
      - include add_sub_extended_reg

v8 -> v9 (ajb):
      - actually use extended register for offset

v9 -> v10 (ajb):
      - add CC support to add_sub_reg

v10 -> v11 (pmm):
      - split arith_CC into gen_add/sub_cc functions
      - rewrite with newer version of flag code

v11 -> v12 (ajb):
      - move to using the new read_cpu_reg helper.

v12 -> v13 (ajb):
      - fix bug with signed shifting...

v13 -> v14 (ajb):
      - merge with latest

v14 -> v15 (ajb):
    - generate un-allocated for
      - invalid shift_type
      - invalid shift_amount for 32bit

v15 -> v16 (ajb):
    - new cpu_read_reg_sp function
    - fix add/sub logic to new CC api

v16 -> v17 (ajb):
    - fix comment style

v17 -> v18 (pmm):
    - comment fixups for helper functions
    - fix spacing in trinary
    - catch un-allocated encodings
target-arm: A64: add support for ldp/stp

This patch support the basic load/store-pair instructions and includes
the generic store helper functions:

  * do_gpr_st()
  * do_fp_st()
  * do_gpr_ld()
  * do_fp_ld()
  * gen_check_sp_alignment()

The last function gen_check_sp_alignment() is a NULL op currently but
put in place to make it easy to add SP alignment checking later.

This was split out from the more substantial ldarx implementation during
the re-factoring of the decoder.

from Alexander Graf <agraf@suse.de> aarch64 series 11/60
from Alexander Graf <agraf@suse.de> aarch64 series 12/60

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 -> v3:
   - use extract32/sextract32 instead of get_bits and get_sbits
   - drop get_reg()
   - open code get_reg()

v3 -> v4
   - split from bigger patch (non vector)
   - better naming?

v4 -> v5
   - added vector/fp support
   - use decent size for index

v5 -> v6
   - fix dodgy offset calculation into fpregs

v6 -> v7
   - add SP alignment check
   - fix comment style

v7 -> v8
   - fix gen_mem_index to be less hacky.

v8 -> v9
   - fix line wrapping of function signatures
   - function renaming as they are more generic
   - merge load/store pair commit
   - a little shuffling of allocations
target-arm: A64: add support for movi instructions

This patch adds emulation for the movi instruction. This includes the
various movn, movz and movk forms.

From Alexander Graf <agraf@suse.de> aarch64 series 28/60
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 -> v3:
   - use extract32/sextract32 instead of get_bits and get_sbits
   - open code get_reg()

v3 -> v4 (ajb):
   - applied RH's constant folding comment
   - move cpu_reg allocation to top

v4 -> v5 (ajb):
   - fix comment, made invalid opcode explicit by using switch
   - ensure we invert the right one

v5 -> v6 (ajb):
   - risu fixes
   - ensure we correctly zero extend for 32 bit
   - ensure we are unallocated() for invalid shift amounts

v6 -> v7 (ajb):
   - fix up comment style

v7 -> v8 (pmm):
   - minor stylistic fixes
target-arm: A64: add support for ld/st unsigned imm

This adds support for the basic forms of ld/st with an unsigned
immediate offset. This was split from the original patch from Alexander
due to re-factoring due to the changes in the decoder.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (pmm):
   - hoisted is_vector test into function

v4 -> v5 (pmm):
   - added support for ld/st of FP regs
   - fixed some tcg temp leaks

v5 -> v6 (ajb):
   - fixed signed extension on loads

v6 -> v7 (ajb):
   - move tcg_rt to more local scope

v7 -> v8 (pmm):
   - fix for broken compilers
target-arm: A64: add support for ld/st with reg offset

This adds support for the load/store forms using a register offset. This
was split out from the original patch due to re-factoring changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   fixed reg extension

v4 -> v5 (pmm):
   moved is_vector test into handle func
   fix invalid asset on opt==6

v5 -> v6 (ajb):
   fix temp lead in handle_ldst_reg_roffset

v6 -> v7 (ajb):
   use new gpr_ld api
   new cpu read api

v7 -> v8 (ajb):
   add vector support

v8 -> v9 (ajb):
   fix comment style
   check sp alignment
   load rn direct into tcg_addr

v9 -> v10 (pmm):
   fix comments
   remove bogus asserts and catch unallocted earlier
target-arm: A64: add support for ld/st with index

This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form. This was split out of
the original patch due to re-factoring changes.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb)
   - fix ld/st reg indexed_imm to correctly extend and shift

v4 -> v5 (ajb):
   - fix silly bug with extracting register

v5 -> v6 (pmm):
   - move is_vector test into handler.

v6 -> v7 (pmm):
   - add un-scaled imm9 version

v7 -> v8 (ajb):
   - use new gpr_ld api

v8 -> v9 (ajb):
   - add vector support

v9 -> v10 (ajb):
   - fix comment style
   - add check sp alignment check
   - load tcg_addr directly from rn
   - only get tcg_rn when writeback

v10 -> v11 (pmm):
   - fix comments

NOTES:

I suspect we're going to want to fold the 'load/store unprivileged'
insns into the same imm9 decode, so I have left the door open for that.
However since we shouldn't see those for userspace code we can ignore
it for the moment.

-- PMM
target-arm: A64: add support for svc instruction

This patch adds emulation for the syscall (svc) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 -> v3:
  - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):
  - ported to new decode skeleton

v4 -> v5 (ajb):
 - fixed stupid decode error

v5 -> v6 (ajb):
 - fix svc from peters tree.
target-arm: A64: add support for 3 src data proc

This patch adds emulation for most of the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.

Add support for various 3 source data processing instructions.

From Alexander Graf <agraf@suse.de> aarch64 series 49/60

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

---

TODO fix up attributions, commit message

v3 -> v4 (pmm):
   - ported to into new decoder
   - cleaned up to match current fn name conventions
target-arm: A64: Floating point <-> integer conv

This is kinda from suse patch 52 but I ended up rewriting
it pretty thoroughly and with a view to comments made on the mailing
list w.r.t the silliness of double stores to the fpu reg memory).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Inspired-by: Alexander Graf <agraf@suse.de> aarch64 series 52/60

---

v1 -> v2 (ajb):
   fixup comment style
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60

---

v3 -> v4 (ajb):
   - use new ld_gpr api

v4 -> v5 (ajb):
   - fixup commenting style
target-arm: A64: WIP support for ld/st exclusive

XXX: not up-streamable as is - still has failure modes

This implement exclusive loads/stores for aarch64 like for arm32 and
ppc.  loads remember the address and loaded value, and stores throw
an exception which uses those values to check for equality in a proper
exclusive region.

AArch64 also implements new aquire/release loads/stores without the
exclusive part, which merely imposes an ordering on memory operations.
As we run on just one CPU, that's not necessary, but could be done
e.g. by a simple heavy barrier insn.

from Alexander Graf <agraf@suse.de> aarch64 series 12/60
 and Michael Matz <matz@suse.de> aarch64-1.6 branch
 and Peter Maydell <peter.maydell@linaro.org> aarch64 clean-up

---

v3 -> v4 (ajb):
   - use new gpr_ld API

v4 -> v5 (ajb):
   - merge in later fixes from Matz
   - fix bug with using ZR for status
   - add sp alignment check
   - fixup bogus whitespace
squash warning