[PATCH 01/32] arm-trustzone: Start a cleaned up patch series on top
 of Linaro's QEMU release 2013.03

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 02/32] WIP: arm-trustzone: Refine CP register handling

* Separate SECURE_CP flag for selecting the register bank.
* Stubs for generating CP access logs (secure/normal world)

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 03/32] WIP: arm-trustzone: Simplified handling of CP register
 banks.

Unbanked registers (default) do not require any special
handling. Registers with a secure and a normal world version
are instantiated twice, to allow clean integration with the
ARM_CP_OVERRIDE override mechanism.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 04/32] WIP: arm-trustzone: Support simple banked registers
 using banked_uint{32,64}_t

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 05/32] WIP/BUG: arm-trustzone: Enable banked of CP registers.

NOTE: S/N access gets confused :(

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 06/32] WIP: arm-trustzone: Hunting the banking bugs - again
 :(

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 07/32] FIX: arm-trustzone: Use the proper bit shift for
 SECURE_CP mask.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 08/32] FIX: arm-trustzone: Add the missing SCR.NS bit :)

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 09/32] FIX: arm-trustzone: Implement some privileged
 loads/stores correctly.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 10/32] FIX: arm-trustzone: Specify the correct register in
 CONTEXTIDR cp_reginfo.

The underlying bug is present in the Linaro 2012.08 release (where it went
seems to go unnoticed due to different handling of contextidr_write).

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 11/32] WIP: arm-trustzone: Cleanup IRQ/FIQ entry code

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 12/32] WIP: arm-trustzone: Add stub models of TrustZone
 controllers (BP147, TZC380)

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 13/32] WIP: arm-trustzone: Prepare get_phys_addr for
 TrustZone memory checks.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 14/32] WIP: arm-trustzone: Add physical memory access hook  into ARM MMU emulation.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 15/32] WIP: arm-trustzone: Revised initialisation of TZC380
 and BP147 peripherals

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 16/32] WIP: arm-trustzone: Prototype API for TrustZone
 Protection Controller bit associations.

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 17/32] WIP: arm-trustzone: Add initial experimental results
 with OpenVirtualization

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 18/32] WIP: arm-trustzone: Start some simple test cases

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 19/32] WIP: arm-trustzone: Suppress instantiation of normal
 world CP registers on non-TrustZone CPUs

Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
[PATCH 20/32] WIP: arm-trustzone: First experiments with GDB target
 descriptor generation for CP regs.