msm: camera: Notify application in case of bad state.

In case, the bus overflow keeps happening beyond a
predefined threshold, stop recovery and notify the
user about the error so that camera can be gracefully
shutdown.

Change-Id: Ie87ced67f3876c1500ce905c9f80c23239685fd5
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
msm_serial_hs: Increase rx buffer size to 1024bytes

Increase the UARTDM rx buffer size from 512 bytes
to 1024 bytes. This patch helps to increase the
rx data rates of the clients that uses serial_hs driver.

CRs-Fixed: 514385
Change-Id: I2956020af299dda849cfbef795728da2d8664c77
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
msm: camera: Guard the release of resources using mutex

The critical section of the code related to release needs to be
protected against race conditions.

Change-Id: I2165d37168882c345e2f845df08b74eb49b3cb23
CRs-fixed: 518302
Signed-off-by: Alok Kediya <kediya@codeaurora.org>
Merge "msm: camera: Guard the release of resources using mutex"
Merge "msm_serial_hs: Increase rx buffer size to 1024bytes"
USB: EHCI:  Ensure 10 msec delay between bus states

According to EHCI specification, software must wait for at least 10 msec
after a port indicates that it is suspended before initiating a port
resume.  The current code uses jiffies and fails to give the delay if
suspend and resume happens at the timer tick boundaries.

The correct implementation would be ensuring this delay by using hrtimers
or ktime_get().  This involves changing many drivers.  Hence workaround
it by increasing the state change delay to 2 jiffies.

CRs-Fixed: 521047
Change-Id: I703210cca83d649d1b253e971dfba8f62c6ccb8c
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
msm: spm: modify power collapse seq for kraitv3

High sleep current observed due to L2 cache not going into
power collapse in special cases.

While analyzing, a timing issue was found that can manifest itself when the
clamp signal is asserted during the Krait CPU1 power collapse sequence.
When it occurs, the issue causes an L2 FIFO to falsely believe that it
has data to return to CPU1 when it does not.The condition isnt detected until
later when CPU0 and the L2 attempt to collapse.

This condition keeps the L2 from going idle which keeps it from power
collapsing after both CPUs have collapsed.  This in turn prevents the
RPM from enabling a system low power state (VDD minimization).
The issue is likely process/temp/voltage dependent.

HW team recommended a workaround, the details are as below.

Add commands to the Krait CPU power collapse SPM sequences to assert
Krait CPU reset prior to asserting the CPU clamp signal and de-assert
CPU reset after the CPU clamp is asserted.
Since the CPU clocks are gated (by the first SPM command in the
sequence), and the clamp is applied, the Krait CPU will do nothing
when its reset is de-asserted.

The workaround involves changing both CPU power collapse SPM sequences
(Power Collapse with and without RPM notification).

CRs-fixed: 518750
Change-Id: I62c76f49a96a8cb6ecf67733ae9a7ff1a79a76f7
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
power: pm8921-charger: Add delay after turning on D0 (TCXO) clock

On APQ8064, TCXO cannot be turned off before its warm-up period (4ms).
This is not required on the platform which have a CXO. Add a warm-up
delay after turning on D0 (which turns on the TCXO).

Change-Id: I252372c35a9fdfaf4a9fade1594936b05c1b5745
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Merge "USB: EHCI:  Ensure 10 msec delay between bus states"
Merge "msm: spm: modify power collapse seq for kraitv3"
Merge "msm: camera: Notify application in case of bad state."
Merge "power: pm8921-charger: Add delay after turning on D0 (TCXO) clock"