Arranged format for failsafe default and avoiding unnecessary activity i...

...f endianess is correct
The current refactor is just a cleaningup of the previous code, beside hardening it up and making it simpler for the enduser.
I am however wondering on the endianess issue since FPGA mus produce data in a well defined manner, I hope, possibly little endian.
If it is so (maybe not) then the logic should be adjusted to take care of this fact.