STM32F0: Bugfix: Clear the RCC_CFGR_PLLSRC bit

Replace

    RCC_CFGR &= RCC_CFGR_PLLSRC;

with

    RCC_CFGR &= ~RCC_CFGR_PLLSRC;

RCC_CFGR_PLLSRC is actually just the single set bit and it needs to
be cleared to have HSI/2 as the PLL clock input. See
'STM32F05xxx/06xxx advanced ARM-based 32-bit MCUs', p. 101.