sim_core.c: extended data type to 32 bits for eicall/eijmp instruction.

	modified:   simavr/sim/sim_core.c
Merge pull request #21 from bsekisser/sim_core_eicall_eijmp_bugfix

sim_core.c: extended data type to 32 bits for eicall/eijmp instruction.
megax8: Added a couple of timer modes

Pretty obvious timer modes were missing...

Signed-off-by: Michel Pollet <buserror@gmail.com>
twi: Added first bit of slave support

Need the slave support for TWI, will add bits as I go along

Signed-off-by: Michel Pollet <buserror@gmail.com>
misc: Traces updates

Applies naming convention to globals, types etc.
elf: Redone the symbol loader

Old symbol loader had been geared for the 'trace' functionality, and was
partitularly bad since it didnt know the size of the code it was
loading.

New version loads a (sorted) array of symbols, and let the firmware
loader code deal with the old 'codeline' array. The new loaded symbol
table can be used separately (board code can look into it).

Also changed the avr_symbol_t to inline the symbol name, instead of
using a separate pointer.

Signed-off-by: Michel Pollet <buserror@gmail.com>
twi: Prototype support for slave mode

This is not working fully right now.

Also changed the MOSI/MISO names for the IRQ, as they make no sense when
using the master/slave TWI.

Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Added atmega32
Merge pull request #24 from sealibora/master

cores: Added atmega32
fifo: Updated to latest version

This version was lagging quite a bit; this one has memory barriers, and
an updated write()

Signed-off-by: Michel Pollet <buserror@gmail.com>
ioports: Redid the DDR handling logic

Now supports an "external" simulation of a pullup/down, this
resets the outgoing IRQ for pins to a default that can be
specified.

Signed-off-by: Michel Pollet <buserror@gmail.com>
elf: Added support for external pullup/down

Added a new "mmcu" section to allow firmwares to specify what
IRQ value should be set when a pin is marked as input

Signed-off-by: Michel Pollet <buserror@gmail.com>
sim_core.c: fix implimentation of inc/dec to match specification

the avr instruction manual states that overflow be set _before_ the operation takes place, however the core tests based on the result.  values checked adjusted accordingly.

bug find credit goes to: Shay Green <gblargg@gmail.com>
sim_core.c: fix implimentation of bld instruction

prior implimentation of the bld insruction was ORing bit with T, rather than replacing.

bug find credit goes to: Shay Green <gblargg@gmail.com>
sim_core.c: fix implimentation of ror instruction

prior implimentation just cleared n flag while specification states n should be set or cleared according to the most significant bit of the result.

bug find credit goes to: Shay Green <gblargg@gmail.com>

	modified:   simavr/sim/sim_core.c
sim_core.c: fix implimentation of muls instruction

specification for muls insruction states 2 cycles, not one as implimented.

bug find credit goes to: Shay Green <gblargg@gmail.com>

	modified:   sim_core.c
Merge pull request #27 from bsekisser/sim-core-inc-dec-bugfix

sim_core.c: fix implimentation of inc/dec to match specification
Merge pull request #28 from bsekisser/sim-core-bld-bugfix

sim_core.c: fix implimentation of bld instruction
Merge pull request #29 from bsekisser/sim-core-ror-bugfix

sim_core.c: fix implimentation of ror instruction
Merge pull request #30 from bsekisser/sim-core-muls-bugfix

sim_core.c: fix implimentation of muls instruction