lib: genalloc: Change chunk allocation to vmalloc

Change the chunk allocation from kmalloc to vmalloc for
allocations greater than a page. This allows large
chunks to be allocated from physically non-contiguous
memory and increases the chance of the allocation
succeeding.

CRs-fixed: 387655
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 0614b96dc8e4c8a0dd0db41aec5a79daa3bdf091)

Conflicts:

	lib/genalloc.c

Change-Id: Ic0dedbad9d277d0842591b1f075ce3b80c8c05de
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: idle-v7.S: Warmboot support for NR_CPUS >= 2

The change supports save/restore of processor state during warmboot when
the number of cores is greater than 2. The current version supports two
cores only.

Change-Id: Icd23f10cde00a5dbe0abc1a76f1555f8834053a3
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle-v7: Power collapse Krait with caches enabled

The SCTLR[C/I] bits do not need to be cleared when entering
power collapse on Krait CPUs.

Change-Id: Ic33b227fe55a87e10aab46e6a30f44cc400ccfbb
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: idle-v7: Remove redundant cache clean

Cleaning the register save area is not necessary if we are
already cleaning the entire cache. Eliminate the redundant
cleaning operation to reduce power collapse latency.

Change-Id: I3651083f147874fd6003cfe12b07861689ca77cc
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: idle-v7 : Restore context for NR_CPUS >= 2 when PC fails

When there is a pending interrupt and the core executes WFI
instruction, the SPM would not trigger its state machine and would
bail out. The instructions after the WFI instruction will be executed.
The context calculation need to take care of getting the right context
to restore.

Change-Id: Icda4abe68503250f27b8c9b89891318beab86a7b
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: pm: save registers to noncached area before pc

The power collapse path is simplified if a noncached area is
used for the purpose of saving register state prior to power
collapsing. This is especially beneficial in the case of targets
with an outer cache, where the process of cleaning the register
state would require complex operations.

Change-Id: I9edac28e4091548e2843fc87c89e3451df2b6ae9
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
thermal: Don't limit CPU frequency after msm_thermal is disabled

There may be an outstanding task to check for threshold crossing
when msm_thermal is disabled and CPU is restored to maximum
frequency. This task can get scheduled after the maximum frequency
is restored, and result in another mitigation that pins CPU
frequencies to 918mHz. This happens in the case that the final
temperature was still above the max temperature threshold.
This patch ensures any outstanding tasks are cancelled and flushed
before finally restoring the CPU frequencies.

CRs-fixed: 351614
Change-Id: Ifce00b379989b78856803ac09c7403207f5c998b
Signed-off-by: Eugene Seah <eseah@codeaurora.org>
msm: thermal: Simplify kernel thermal safeguard mechanism

Using CPUFreq policy objects and setting the max frequency limit by
overriding the policy->max node, leads to race/overwrite conditions with
an user trying to use the scaling_max_frequency node.

The thermal limits are directly communicated to the 'msm' cpufreq driver
and use the cpufreq_update_policy() to ensure that the frequency is
limited as per the thermal safeguard requirements.

CRs-fixed: 370343
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 9181436c8d688480ded367557b4b9b012b1881b2)

Change-Id: I5c4ceaac00c6dcd91eb207c555519f9c5fd08d9b
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
msm: cpufreq: Add API to allow limiting of min and max cpu frequencies

CPUFreq provides scaling sysfs nodes to set min and max frequencies, but
there are times when the operating range has to be controlled
irrespective of the scaling limits, to ensure the thermal stability of
the device.

The API allows kernel thermal safeguards to pitch in and limit the
frequencies.

Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 696a561c5bbc4733476db16be6f05fd92dee9a71)

Change-Id: I7faa1205948b81a23d24a3b29bdedc98a07a5861
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
arm: show present cpu instead of online cpu in /proc/cpuinfo

Some userspace applications use /proc/cpuinfo to determine how many CPUs
the system has. CPU hotplug can offline a CPU at runtime and causing the
offline CPU not present in /proc/cpuinfo if we only show online cpu in
/proc/cpuinfo.

CRs-Fixed: 354430
Signed-off-by: Jin Hong <jinh@codeaurora.org>
(cherry picked from commit 1e28794d0ff00fc6567d68b5b4e863b0745cfe20)

Change-Id: I3b38472b690bb3dba67ada74f60cce79ed0b2a7d
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
USB: f_mtp: Fix corner cases in MTP driver while syncing

Currently if USB composition switch happens while file transfer is
happening either from/to device, ep_queue fails and sets device state
to ERROR even if device state is already set to OFFLINE in function
disable call.

As part of ioctl call, if the state is not offline, moving the device
state to READY and returning the error. Since the device state is marked
as READY, the next write call tries to queue the request to hardware and
is blocked and due to this, userspace is not calling the release function.
Hence next mtp open fails even after cable reconnection.

CRs-Fixed: 360409
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
(cherry picked from commit 0097223c586963c9904c90803eaa5ee878565fbe)

Change-Id: I9d11cfd44f98a4fcf4e95f75462904bfb2b6cb2d
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
msm: cpufreq: Fix store_powersave_bias to account for sync' CPUs.

Current code assumes that all online CPUs runs their own timers to
collect CPU samples for demand based switching (dbs). But in case of
synchronous CPUs, ondemand governor registers only one timer at init
time because both CPUs are accounted in the same timer call. Hence
trying to restart/cancel dbs timers for all online CPUs is not legal
for these CPUs. This change fixes above function to restart/cancel
timers only once for group of synchronous CPUs.

Change-Id: I23f1697783a65f125679a07a076620e8fa5e62d5
Signed-off-by: Krishna Vanka <kvanka@codeaurora.org>
msm: smp: Remove WFE/SEV from secondary core bootup

During the cold boot path once the secondary core is released
out of reset we keep looping for the pen release variable.
The wfe+sev in this path are just unnecessary as they provide
negligible power savings, and the latency cost is not worth it.
During the hotplug path the secondary core will be in wfi and
only an interrupt will be able to bring the core out.
Removing the wfe effectively lowers the hotplug latency.

CRs-Fixed: 372035
Change-Id: Ife39339ec09181a4ca3cd3755733662bd8842c0c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
tty: hold lock across tty buffer finding and buffer filling

tty_buffer_request_room is well protected, but while after it returns,
 it releases the port->lock. tty->buf.tail might be modified
by either irq handler or other threads. The patch adds more protection
by holding the lock across tty buffer finding and buffer filling.

Signed-off-by: Alek Du <alek.du@intel.com>
Signed-off-by: Xiaobing Tu <xiaobing.tu@intel.com>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CRs-Fixed: 387308
Signed-off-by: Vamsi Krishna <vskrishn@codeaurora.org>
(cherry picked from commit 09236b0fbea5268bce3568d974654f8d9ddb83ec)

Change-Id: If383e12d6e65cfde1e2df2e65df8c3a4c30385ed
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
staging: android: lowmemorykiller: Add config option to support oom_adj values

The conversion to use oom_score_adj instead of the deprecated oom_adj
values breaks existing user-space code. Add a config option to convert
oom_adj values written to oom_score_adj values if they appear to be
valid oom_adj values.

Change-Id: I68308125059b802ee2991feefb07e9703bc48549
Signed-off-by: Arve Hjønnevåg <arve@android.com>
staging: android: lowmemorykiller: Don't count reserved free memory

The amount of reserved memory varies between devices. Subtract it
here to reduce the amount of devices specific tuning needed for the
minfree values.

Change-Id: I466ae8b18f5972f6f6d8b5a7d8c4ae69660de53a
Signed-off-by: Arve Hjønnevåg <arve@android.com>
staging: android: lowmemorykiller: Change default debug_level to 1

The select...to kill messages are not very useful when not debugging
the lowmemorykiller itself. After the change to check TIF_MEMDIE
instead of using a task notifer this message can also get very
noisy.

Change-Id: Ice171c25801d6faa454b885a23b24b002423b754
Signed-off-by: Arve Hjønnevåg <arve@android.com>
hardlockup: detect hard lockups without NMIs using secondary cpus

Emulate NMIs on systems where they are not available by using timer
interrupts on other cpus.  Each cpu will use its softlockup hrtimer
to update a per-cpu timestamp and then check the timestamp on the
next cpu.

The emulation uses the softlockup threshold instead of the hardlockup
threshold because the implementation runs at the same resolution as
the softlockup detector.

This patch is useful on systems where the hardlockup detector is not
available due to a lack of NMIs, for example most ARM SoCs.
Without this patch any cpu stuck with interrupts disabled can
cause a hardware watchdog reset with no debugging information,
but with this patch the kernel can detect the lockup and panic,
which can result in useful debugging info.

Change-Id: I3e6de6da27183b2a0a73a390e394f95a945856d9
Signed-off-by: Colin Cross <ccross@android.com>
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem.  The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily optimized
sha-1 implementation used in git.  With the git sha-1 implementation, we
see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

  Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

  Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that it only
needs 64 bytes of stack for the workspace while the original kernel
implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
Cc: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
Cc: Nicolas Pitre <nico@cam.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arm: remove "optimized" SHA1 routines

Since commit 1eb19a12bd22 ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>