reset clk2x_off phase for ddr to 250 deg.

all playing around with it did not help. memtest output currently looks
like the following (columns are: address, read/actual, written/desired):

18a8 56d156d1 64a056d1
18ac a1fc64a0 b593a1fc
18b0 952b952b 1914952b
18b4 a88e1914 471ca88e
18b8 16951695 b9ea1695
18bc 76f0b9ea 26de76f0
18c0 9d8f9d8f 768e9d8f
18c4 eda2768e 776aeda2
18c8 90999099 1c5d9099
18cc 41241c5d 13bd4124
18d0 9a339a33 1839a33
18d4 19f60183 ce8919f6
18d8 48dd48dd e2c348dd
18dc b498e2c3 acf6b498

MSW ends up being LSW
LSW ends up being previous HSW or current LSW

~180 clock phase shift?
dqs mixup?

funny thing is, that with mw/mr from the bios everything is dandy