nbody: rename SSE implementations to "SIMD" to allow for platform-specific code

Doesn't make sense to call it "SSE" if it's NEON or AltiVec for example.

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: adding AltiVec SIMD implementation for Power architecture builds

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: add nbody_CPU_SIMD.h

Making SIMD optional by platform.

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: move -O3 from CFLAGS to NVCCFLAGS

CFOPTIMIZE is non-nvcc specific (e.g. nvcc doesn't understand '-Os'), and we
need -some- optimization flag passed to nvcc without passing it to GCC as well.

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: add -maltivec to CXXFLAGS if on PowerPC and NO_SIMD isn't set

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: drop headers redundant due to nbody_CPU_SIMD.h

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: add ARMv7a NEON implementation

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: switch back to O3 for optimization

While x86 does fine (and in some ways better) with -Os, ARM has a lot of
performance issues (6x performance hit with reference implementation) when
biased for size optimization:

ARMv7hf with GCC 4.7.2 (-Os):
    CPU_AOS: 2663.05 ms = 1.575x10^6 interactions/s (Rel. error: 0.000000E+00)
    CPU_AOS: 2662.69 ms = 1.575x10^6 interactions/s (Rel. error: 0.000000E+00)
    CPU_AOS: 2666.26 ms = 1.573x10^6 interactions/s (Rel. error: 0.000000E+00)

ARMv7hf with GCC 4.7.2 (-O3):
    CPU_AOS: 466.88 ms = 8.984x10^6 interactions/s (Rel. error: 0.000000E+00)
    CPU_AOS: 466.87 ms = 8.984x10^6 interactions/s (Rel. error: 0.000000E+00)
    CPU_AOS: 466.89 ms = 8.983x10^6 interactions/s (Rel. error: 0.000000E+00)

Also adding -ffast-math, which has a sizable impact on the SIMD variants.

Signed-off-by: Steven Noonan <steven@uplinklabs.net>
nbody: add -fno-strict-aliasing to prevent insane optimizations

Signed-off-by: Steven Noonan <steven@uplinklabs.net>