Merge "msm: adsprpc: RPC driver between apps and adsp"
Merge "msm: adsprpc: include msm-specific ion header file"
Merge "msm: adsprpc: Incorporate coding style comments"
Merge "msm: Move adsprpc into drivers"
Conflicts:
Merge "msm_fb: display: restore previous mdp bandwidth when resume"
msm: vidc: Correct the display size of small resolution clips

We change the frame height in the decoder to MDP_MIN_TILE_HEIGHT
for the videos with frame height less than 96. Due to which these
videos were not being displayed properly. This change fixes the
display change.

Change-Id: I7acc74742a8cfbdfc79b02bd20bb9109f4389fa2
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Vidc: Treat Non-IDR frame type error as bit stream error

Hardware error is being generated from driver when video
core returns NON IDR frame type error during thumbnail
decoding. This change handles this error by treating
it as BIT_STREAM_ERR.

Change-Id: I16a19eea679d42a22b336d6ebbd0bd1f57c0a8a4
CRs-fixed: 414858
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
usb: mdm_bridge: Fix race between disconnect and I/O completion handler

There is a possibility of race between device disconnect and I/O
completion handler. In this case disconnect frees bridge device
memory in thread context and I/O completion handler uses already
freed bridge device memory in interrupt context. Hence allocate
bridge device memory at the time of driver load and free it
during unload. Also, do not anchor interrupt and read urb and
unlink them synchronously to avoid accessing transfer buffers
associated to these urbs when driver disconnect frees them.

Guard the race condition by:-
1) Adding check for usb device disconnect state in the I/O
completion handler to avoid further processing I/O completion.

2) Unlinking tx urbs synchronously since asynchronous unlinking
results in the same race condition.

CRs-Fixed: 447591
Change-Id: Iae4c2a1920c16fcf3e1728144a7cfe6ca66c7705
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>

Conflicts:
	drivers/usb/misc/mdm_data_bridge.c
ASoC: msm: Resume writes only for start command

For compressed and LPA drivers, set pending_buffers flag to 1 only if the client
issues a trigger_start command, not a pause_release command. This flag
is used to initiate writes to the dsp.

Change-Id: I503156863646210b460613a0b9a26a6bfb8854ed
CRs-Fixed: 442269, 449126
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
usb: gadget: Unclaim endpoints upon disconnect

HSIC data driver is not setting endpoint driver data to NULL
upon disconnect. This causes endpoints to remain claimed at
the time of function driver unbind. Endpoints will remain
unusable when driver bind happens later. This can result in
function bind failure due to lack of available(unclaimed)
endpoints if there is a series of driver unbind and bind
happens. Hence after disabling endpoint set driver data of
the endpoint to NULL upon disconnect.

CRs-Fixed: 449814
Change-Id: I8656e15ac26dfc6f4f6679b7ee2bba0bf935f0d6
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
msm: kgsl: Don't change the sglen of the memdesc if allocation fails

If the page_alloc loop fails, we changed the length of the scatterlist
for the memdesc to the last good page so we could have an efficient
loop through kgsl_sharedmem_free.  Unfortunately, we were also using
the sglen to decide between using kmem or vmalloc memory for the sg
list in the first place. There is a chance that one could start out
with a large sg list from vmalloc, but if it failed early, then we
could truncate the size and attempt to kfree it.

Zero the stlist at init time and use a length == 0 as an indicator
that the list might be truncated.
CRs-Fixed: 443441

Change-Id: Ib48a08c69a7bbfc69b92f09e83fc80f9bdedffe0
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>

Conflicts:
	drivers/gpu/msm/kgsl_sharedmem.c
Perf: Make L1 PMU IRQ name target independent

Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.

Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add generic IRQ handlers for ARMv7 PMU's

For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.

Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Let platforms decide IRQ request methods.

This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.

Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.

The default behavior is maintained for all other ARM targets.

Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: Perf: Differentiate between L1 and L2 PMU IRQs

The L2 perf code shares some resource reservation functions
with the L1 perf code. In these functions, use defaults
only if they're not defined for the L1 and L2.

Change-Id: I5a390aa0085694466800db78b51837556aa12cdd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Assign proper routine to free IRQ

If the platform descriptor does not provide
its own free_irq function, default to the fallback
version.

Change-Id: I185186bf68b79e2dbfba77b0de66eb4daaf32fb8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: Relax Column exclusion checks for L2CC events

Identical L2CC events with the same register, code and group
can be set up with individual origin filters. The hardware
restricts counting only for identical register and group settings
but a different value for the event code.

Detect such identical events and let them pass the constraint
checks.

Change-Id: I609defb5c5b070b1007b2e7db9e2d8315d2ba1d7
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: add debug patch logging framework

Provide a mechanism to track which msm perf patches
are present in a kernel. Some kernel branches do
not include all patches which causes problems trying
to debug perf issues. This framework provides a way
to keep track of which patches have been included
in a build.

Change-Id: Ib8ef311454564c4609d94decd93e039c80104275
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's

The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.

Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>