deassert write ack after last transaction

This fell out it in commit
37b0b5c74da35a89feb627c159c0798c725a5d09
fix wishbone burst writes

This reinserts it
dpram_altera: make the dpram less technology dependant

read_during_write_mode_port parameter is only available on
M9K, M144K, M10K and M20K memory block types.

This parameter configure the type of new data behavior for
same-port RDW. When byte enable is applied, you can choose
to read old data, or ‘X’ on the masked byte.

As there is no RDW on this dpram in our case, we can safely
remove this parameter so the memory instanciation is compatible
with all kind of memory blocks.

More info: http://www.altera.com/literature/ug/ug_ram_rom.pdf

Also remove intended_device_family to make the instanciation
looks more generic.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'dpram' of https://github.com/fjullien/wb_sdram_ctrl
Wait for refill to end before writing into bufram

When doing burst writes, and the writes matches the address
that's in the bufram, it's not enough to initially check that
the first write address is "clean" (i.e. has been written into
the bufram from the read side, in case of a refill).
Instead check that all of the slots in the bufram is clean before
performing the write into it.
sdram_ctrl: Set value of ba during reset
Add test bench for wb_sdram_ctrl
Merge branch 'master' of https://github.com/skristiansson/wb_sdram_ctrl
dpram_altera: make the instantation even more generic

When the device familly is not specified, modelsim chose the
default Stratix familly. Then, it throws up:

 Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in
 Stratix device family

This patch let clock_enable_xxx parameters get their default value.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>