Align double array backing store during compaction and mark-sweep promotion.

1st (of 3) CL's to ensure complete alignment of FixedDoubleArrays.

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Enable double alignment for constructed arrays.

2nd (of 3) CL's to ensure complete alignment of FixedDoubleArrays.

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MIPS: Ensure double aligned allocations through runtime routines.

3rd (of 3) CLs to ensure complete alignment of FixedDoubleArrays.

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MIPS: Enable aligned keyed stores and loads for double arrays.

Provide ~20% performance improvement in Navier-Stokes benchmark, by using
true load/store double (ldc1/sdc1) instructions.

These instructions require double-aligned memory address. Since doubles are not
generally aligned in v8, we historically have used a workaround using a pair of
32-bit loads/stores (lwc1/swc1), which is slow.

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