Blocked use of VREF on main board USB bank, as the pins are "slow" due to extra capacitance. Had to move one TX PIPE signal off a VREF pin.
Connected VCCIO to main board USB.
Connectoed DDR2 CLK* pins.
Added note about termination strategy for DDR2 buses.
Removed VREF pin from DDR2 FPGA sheet -- VREF needs to be generated locally.