tcg-s390: Fix movi

The code to load the high 64 bits assumed that the insn used to
load the low 64 bits zero-extended.  Enforce that.
tcg-s390: Properly allocate a stack frame.

Set TCG_TARGET_CALL_STACK_OFFSET properly for the abi.  Allocate the
standard TCG_STATIC_CALL_ARGS_SIZE.  And while we're at it, allocate
space for CPU_TEMP_BUF_NLONGS.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Remove useless preprocessor conditions

We only support 64-bit code generation for s390x.
Don't clutter the code with ifdefs that suggest otherwise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Implement add2/sub2 opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Implement mulu2_i64 opcode

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Implement movcond opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Implement deposit opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Remove constraint letters for and

Since we have a free temporary and can always just load the constant, we
ought to do so, rather than spending the same effort constraining the const.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Use risbgz for andi

This is immediately usable by the tlb lookup code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Cleanup argument shuffling fixme in softmmu code

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Use load-address for addition

Since we're always in 64-bit mode, load address performs a full
64-bit add.  Use that for 3-address addition, as well as for
larger constant addends when we lack extended-immediates facility.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Use all 20 bits of the offset in tcg_out_mem

This can save one insn, if the constant has any bits in 32-63 set,
but no bits in 21-31 set.  It never results in more insns.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-s390: Fix merge error in tgen_brcond

When the TCG condition codes were re-organized last year,
we failed to update all of the "old-style" tests for unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>
virtio-9p: Fix virtio-9p no longer building after hw-dirs branch merge

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Message-id: 1365495755-10902-1-git-send-email-hdegoede@redhat.com
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
migration: set f->is_write and flush in add_to_iovec

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
migration: use a single I/O operation when writev_buffer is not defined

The recent patches to use vectored I/O for RAM migration caused a
regression in savevm speed.  To restore previous performance,
add data to the buffer in qemu_put_buffer_async whenever writev_buffer
is not available in the QEMUFile.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
migration: drop is_write complications

The same QEMUFile is never used for both read and write.  Simplify
the logic to simply look for presence or absence of the right ops.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
migration: simplify writev vs. non-writev logic

Check f->iovcnt in add_to_iovec, f->buf_index in qemu_put_buffer/byte.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
tci: Use 32-bit signed offsets to loads/stores

Since the change to tcg_exit_req, the first insn of every TB is
a load with a negative offset from env.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off by: Stefan Weil <sw@weilnetz.de>
tci: Use a local variable for env

Since we have total conversion away from global AREG0, we do not
need a global variable named "env".  Retain that name as the
function parameter inside the interpreter.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off by: Stefan Weil <sw@weilnetz.de>