[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores.  This was already being done for loads.

Unfortunately, it is rather difficult to create a test case for this issue.  It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8