target-arm: aarch64: add support for 1-src REV insns

this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: aarch64: add support for bitfield insns

this patch supports C3.4.2 Bitfield instructions
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 31/60
host-utils: add clrsb32/64 - count leading redundant sign bits

this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
target-arm: aarch64: add support for 1-src CLS insn

this patch adds support for the CLS instruction.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From the SUSE patches
target-arm: aarch64: add support for logical (immediate) insns

this patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
It also includes a way to access the registers when
register 31 means SP.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, minor function renaming,
          removed a TCG temp variable]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 29/60