Also generate 20MHz and 10MHz clocks from the PLL (2x and 1x pixel clocks to the 10x pixel clock running at 100MHz).
Add empty hdmi_out pcore. It is an AXI-Burst Master with 3 software registers (base_frame address, stride length, debug).
Add dvi_encoding source files to hdmi_out pcores.
Connect TMDS, TMDSB and pixel clock signals. TMDS and TMDSB come from pins. Pixel clocks come from the clock_generator PLL.