gpu: pvr: Update to DDK 1.8@794370

Change-Id: I403eb902947b552d5b17260e05b8d5543d99c977
gpu: pvr: Update to DDK 1.8@795947

Change-Id: I62fe8e0f0c5f4046a4852d8dfb92c8b0991df378
gpu: pvr: Update to DDK 1.8@796887.

 - Re-introduce DC refcounting fix, which makes an unrelated (and
   unfixed) problem more reproducible.
 - Fix a bug where the driver would not wait for propagation (during
   power transitions) before performing a soft reset.

Change-Id: I192e23f652dc01eb5f08a0abd48e156564fd0bb5
gpu: pvr: Update to DDK 1.8@808799

 - Fix a bad pointer dereference in services DC.
 - Correct GPL license text in two files.

Change-Id: I0eacdabd5f690969a372bdd88b8d0e7bc2b775ff
gpu: pvr: Update to DDK 1.8@813213

 - Add PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND feature for Crespo MapPage()
   crash bug investigation. This will write-protect the MMU pagetables
   when the SGX driver is not modifying them.

Change-Id: I450ead2b020d42dde14522b46c06f63eb75ff6b5
gpu: pvr: Switch on MMU pagetable write-protection.

Make the SGX MMU page tables read-only when the SGX driver has
finished writing them. Should catch other drivers writing to the
page-table memory when they do not own it.

Change-Id: I49800be0188878f7992d0a4d72360761c6c74007
gpu: pvr: Update to DDK 1.8@840215

Change-Id: I899b6a4ed9e88a0e5c4c2e426aee4e11de846a14
Revert "gpu: pvr: Switch on MMU pagetable write-protection."

This reverts commit b8f7c03589e2d0f0b98a56c80c4ee0f42ad40df8

Imgtec now have collected enough info to fix their bug.

Change-Id: I0576665064ffad3473d3716c37208032278d246d
Signed-off-by: JP Abgrall <jpa@google.com>
gpu: pvr: Update to DDK 1.8@869593

 - Fix a bug in the PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND feature (b/6195660)
   which caused an assert to go off when the driver attempted to make GPU
   pagetable memory read-write.

 - Add missing PVRSRVKernelSyncInfoDecRef calls to error paths.

Change-Id: I21dace59073a38221d838ec74fa70eea92a6a2b4
gpu: pvr: Re-enable MMU pagetable write-protection

This reverts commit b43c0161fbca901e586e9ade321a5d8e616f94b9.
gpu: pvr: Update to DDK 1.8@873556

 - Allow SGX compositions requiring implicit synchronization to correctly
   synchronize with more than 8 buffers. This feature has been tested
   with 16 buffers.
 - Enable kernel driver to decode SGX firmware status codes.
   Fixes http://b/6168368

Change-Id: Ie2d9cc4f739f28aaead8c2c2b85609456b4b2072
gpu: pvr: Update to DDK 1.8@900138.

 - Fixed "XPROC workaround in a bad state" messages, issue
   http://b/5806132.
 - Fixed missing GPL header in sgx_ukernel_status_codes.h.

Change-Id: Id7c73b4367f4534b44e2170c4610803050c7b396
gpu: pvr: Update to DDK 1.8@901807

Change-Id: Iee12a4cbba24269b0a6901324ee2e07b5119a063
gpu: pvr: Update to DDK 1.8@904153

 - Fix http://b/6446135 "eglHibernateProcessIMG slows down.."
   Release the bridge mutex in various places while waiting
   on the hardware. Permits multiple userspace processes/threads
   entering the driver simulataneously in some controlled cases.
 - Fix http://b/6096575 "some gralloc operations are very slow"
   Add a shrinkable pool for uncached memory allocations.

Change-Id: I5a2554b351e10b3b35aaccc0ae943a78c1af673c
gpu: pvr: Update to DDK 1.8@905891

 - Fix some bugs in the newly introduced memory pool code (b/6096575)

Change-Id: Ib505041f98ffedf9ae785c79d49ce719202cacb0
gpu: pvr: Update to DDK 1.8@943950

This is a version number change only, for compatibility with the
user-mode driver.

Change-Id: I0cfc6d73c1a386597f96efa97a3bd2e2d366e760
Revert "gpu: pvr: Update to DDK 1.8@943950"

This reverts commit a4f4aa198065e8d33f86cf3567bb4aba0eac5eef.

The DDK change is not yet qualified as a JB release.
But there is a USB VBUS fix needed.
gpu: pvr: Update to DDK 1.8@945322

This is a version number change only, for compatibility with the
user-mode driver.

Change-Id: I272428a490fbbd18ce9016e92e82829c5dc6b898
gpu: pvr: Add thread safety checks to SGX MMU code.

The SGX MMU code was not designed to be used from multiple driver
threads. One theory is that somehow the driver does sometimes use
the MMU code from multiple threads, which could cause corruption
of meta data.

We must allow PID 1 through because the kernel uses this ID before
userspace is up, and the module_init code interacts with the MMU
subsystem.

Otherwise, check that the outer bridge lock is held. If it is held,
check the PID of the caller matches the PID holding the bridge lock.

Change-Id: I35f42f251316b158576e5d853f8099e24942b4f2
gpu: pvr: Fix a bug that prevented MMU PTs from being dumped.

DumpPT already had a static inline if PT_DEBUG or PT_DUMP
weren't defined, so it shouldn't have been #ifdef guarded.

Furthermore, PT_DEBUG isn't enabled so DumpPT would not have been
called to dump the page tables in one case. This is incorrect as
it should have been called if PT_DUMP was enabled.

Change-Id: I4a0d2a3665b7586a5dfa4390098df4edb6edfe74