Added memory ordering and alignment.

The response region at the server is page aligned so that all the struct KVs
fit into one cache line. Here's what can happen if the struct is across cache
lines:

* The key, value and location fields are in line 1. The req_num field is in
cache line 2.

* The writes take place in order: req_num is written to last.

* However, line 2 is flushed before line 2. The DMA read sees the new value
of req_num but an old value of K, V and L. That's a bummer.