Make PrettyStackTraceEntry use ManagedStatic for its ThreadLocal.

This was somewhat tricky because ~PrettyStackTraceEntry() may run after 
llvm_shutdown() has been called. This is rare and only happens for a common idiom 
used in the main() functions of command-line tools. This works around the idiom by 
skipping the stack clean-up if the PrettyStackTraceHead ManagedStatic is not 
constructed (i.e. llvm_shutdown() has been called).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190730 91177308-0d34-0410-b5e6-96231b3b80d8
[lit] Add an --output option, for writing results in a machine readable form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190738 91177308-0d34-0410-b5e6-96231b3b80d8
Add test for untested path in SimplifyCFG

This case wasn't checked with a pointer condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190739 91177308-0d34-0410-b5e6-96231b3b80d8
Add missing CHECK-LABEL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190740 91177308-0d34-0410-b5e6-96231b3b80d8
Support for misc microMIPS instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
Support for microMIPS DIV instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed bug when generating Load Upper Immediate microMIPS instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the long, long defunct IR block placement pass.

This pass was based on the previous (essentially unused) profiling
infrastructure and the assumption that by ordering the basic blocks at
the IR level in a particular way, the correct layout would happen in the
end. This sometimes worked, and mostly didn't. It also was a really
naive implementation of the classical paper that dates from when branch
predictors were primarily directional and when loop structure wasn't
commonly available. It also didn't factor into the equation
non-fallthrough branches and other machine level details.

Anyways, for all of these reasons and more, I wrote
MachineBlockPlacement, which completely supercedes this pass. It both
uses modern profile information infrastructure, and actually works. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190748 91177308-0d34-0410-b5e6-96231b3b80d8
Fix spelling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190749 91177308-0d34-0410-b5e6-96231b3b80d8
Fix spelling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190750 91177308-0d34-0410-b5e6-96231b3b80d8
Add the remaining Intel SHA instructions

Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused StringRef that no compiler warned about, I wonder why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190759 91177308-0d34-0410-b5e6-96231b3b80d8
Expand the mask capability for deciding which functions are mips16 and mips32
so it can be better used for general interoperability testing between mips32
and mips16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190762 91177308-0d34-0410-b5e6-96231b3b80d8
Prevent assert in CombinerGlobalAA with null values

DAGCombiner::isAlias can be called with SrcValue1 or SrcValue2 null, and we
can't use AA in this case (if we try, then the casting code in AA will assert).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190763 91177308-0d34-0410-b5e6-96231b3b80d8
PPC: Don't restrict lvsl generation to after type legalization

The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190764 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r190764: PPC: Don't restrict lvsl generation to after type legalization

This is causing test-suite failures.

Original commit message:

The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190765 91177308-0d34-0410-b5e6-96231b3b80d8
Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
 data structures.

The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.

Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190766 91177308-0d34-0410-b5e6-96231b3b80d8
Fix alignment of unwind data.

For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).

Reviewed by Anton Korobeynikov, Charles Davis and Nico Rieck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190767 91177308-0d34-0410-b5e6-96231b3b80d8
MC: Add support for '?' flags in .section directives

Summary:
The '?' flag uses the last section group if the last had a section
group.  We treat combining an explicit section group and the '?' as a
hard error.

This fixes PR17198.

Reviewers: rafael, bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190768 91177308-0d34-0410-b5e6-96231b3b80d8
ELF: Add support for the exclude section bit for gas compat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190769 91177308-0d34-0410-b5e6-96231b3b80d8