Added Source/Sink instances for Inner side of Channel interfaces.
Replaced some uses of Circuit with MonadCircuit.
Added example of chaining fifos with (>>>).
Completely replaced Interface system.

Interfaces can now be used in either direction.
This unifies Input/Output into Signal (and Output replaces the Signal
type in Logic) and InChan/OutChan into Channel.
This will also allow Readable to be removed in future.

It may also be possible to define an operator to bind any interface
with its inverted version, which would provide a more general and
useful version of the current (=:) operator.

Currently this uses a slightly awkward Direction constraint, which
must be applied to any direction parameter in Interface definitions.
An alternative to this would be nice, but it is adequate for now.
Removed Bindable and Writable type classes.

(=:) is now only defined for inputs, and (<=:) only for Regs.
Removed Readable, replacing all instances with Output.

This requires the reintroduction of the rd function for Regs.
Arith is replaced with a standard Num instance, and as a result
Constant is removed.
Num functions no longer ommitted by Mantle.Prelude.
ClockReset is now (Ref,Ref). This may be replaced later.
Added more functions to Channel.

chanMap/Zip combine Channels using a function on Outputs.
(>x<) operators combine two Channels with the operator x.
Modified Synchronous to use ExtInputs for Clock and Reset.
Some fixes to Circuit.

Renamed makeCircuit to buildCircuit, since it is different from make.
Fixed newExtOutput creating an input instead.
Modified posedge/negedge to take ExtInputs.
Made Counter generate code, added functions to assist.

buildSync constructs Synchronous by creating a new external clock
and reset.
extern takes an Output and makes an ExtOutput bound to the value.
Added functions to externalise general interfaces.

extSignal creates a new Input/Output bound to a corresponding
ExtOutput/ExtInput.
extIfc creates a new interface where each Input/Output is bound
to a corresponding external reference.

Also tidied extern. This will probably be made to work in both
directions once generalised binding is implemented.
Added generalised binding of interfaces.

(=:) operator is now defined in Interface, and works for arbitrary
pairs of opposing interfaces.
Generalised extern over arbitrary interfaces,

This required some minor changes to other code. The exact reason
for these changes' necessity is not yet understood but they do
not seem particularly significant for the moment.
Renamed onSync to onClock.
Added makeExtern and genComponent.

makeExtern builds a Component by creating an external interface.
genComponent generates Verilog for a component, given a module name.

makeExtern currently returns a Phantom datatype VoidIfc ifc to
ensure that its type signature includes an instance of ifc.
This awkwardness suggests further type refactoring is necessary.