lib: genalloc: Change chunk allocation to vmalloc

Change the chunk allocation from kmalloc to vmalloc for
allocations greater than a page. This allows large
chunks to be allocated from physically non-contiguous
memory and increases the chance of the allocation
succeeding.

CRs-fixed: 387655
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
(cherry picked from commit 0614b96dc8e4c8a0dd0db41aec5a79daa3bdf091)

Conflicts:

	lib/genalloc.c

Change-Id: Ic0dedbad9d277d0842591b1f075ce3b80c8c05de
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
msm: idle-v7.S: Warmboot support for NR_CPUS >= 2

The change supports save/restore of processor state during warmboot when
the number of cores is greater than 2. The current version supports two
cores only.

Change-Id: Icd23f10cde00a5dbe0abc1a76f1555f8834053a3
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle-v7: Power collapse Krait with caches enabled

The SCTLR[C/I] bits do not need to be cleared when entering
power collapse on Krait CPUs.

Change-Id: Ic33b227fe55a87e10aab46e6a30f44cc400ccfbb
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: idle-v7: Remove redundant cache clean

Cleaning the register save area is not necessary if we are
already cleaning the entire cache. Eliminate the redundant
cleaning operation to reduce power collapse latency.

Change-Id: I3651083f147874fd6003cfe12b07861689ca77cc
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
msm: idle-v7 : Restore context for NR_CPUS >= 2 when PC fails

When there is a pending interrupt and the core executes WFI
instruction, the SPM would not trigger its state machine and would
bail out. The instructions after the WFI instruction will be executed.
The context calculation need to take care of getting the right context
to restore.

Change-Id: Icda4abe68503250f27b8c9b89891318beab86a7b
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
msm: pm: save registers to noncached area before pc

The power collapse path is simplified if a noncached area is
used for the purpose of saving register state prior to power
collapsing. This is especially beneficial in the case of targets
with an outer cache, where the process of cleaning the register
state would require complex operations.

Change-Id: I9edac28e4091548e2843fc87c89e3451df2b6ae9
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>