arm: PJ4B: Add specfic version of the cpu_suspend and the cpu_resume

PJ4B needs extra instructions for suspend and resume, so instead of
using the armv7 version, this commit introduces specific versions for
PJ4B.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arm: mvebu: export coherency base register pointer

The coherency registers can be accessed by other subsystems such as
the cpuidle one. In order to avoid to ioremap these registers twice,
this patch adds functions to export the virtual base address and
physical base address of the coherency unit registers.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arm: mvebu: Added new set of register for pmsu

The Power Management Unit Service block also controls the Coherency
Fabric subsystem. This new set of registers is needed for the CPU idle
implementation for the Armada 370/XP, it allows to enter a deep CPU
idle state where the Coherency Fabric and the L2 cache are power down.

This patch also add warnings if one of the base register set can't be
ioremaped.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arm: mvebu: export the pmsu base register pointers

The pmsu base registers can be accessed by other subsystems such as
the cpuidle one. In order to avoid to ioremap these registers twice,
this patch adds functions to export the virtual base address.

Currently there is no concurrent access on this register so there is
no need to protect them.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
cpuidle: mvebu: Add Initial cpu idle support for Armada 370/XP SoC

Add wfi/cpu idle/cpu deep idle power states support for Armada XP SoC.

All the latencies and the power consumption values used at the
"armada_370_xp_idle_driver" structure are preliminary and will be
modified in the future after running some measurements and analysis.

Based on the work of Nadav Haklai.

Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
fix up for cpuidle: mvebu: Add Initial cpu idle support for Armada 370/XP SoC

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arm: dts: mvebu: Add a new set of registers to the PMSU node

The Power Management Unit Service block also controls the Coherency
Fabric subsystem. This new set of registers is needed for the CPU idle
implementation for the Armada XP, it allows to enter in a deep CPU
idle state where the Coherency Fabric and the L2 cache are powerdown.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
DEBUG: add the pm_level=idle paramter on the kernel command line

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>