msm_fb: display: Add proper check to program video TILE framesize

Since video tile frame size register is single buffered, at the time
of transition from low resolution to high resolution video frame,
previous framesize is configured for a cycle, which avoids iommu
page faults.
This logic is not required if previous video frame of the pipe,
is not TILE format.
Add a check to apply the above logic only when previous video frame
of the pipe is also TILE frame.

Change-Id: I782100ed0a89126ca021c8a80ef9eb6f2fb55dda
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
msm: mdp: Revert changes for delaying commit for tiled video

This reverts commits 3ec662e7079cad581e1b6f13a386059b40fa237a and.
bb3d5cf6e59c86dc619332fad568430c737e7a45.
These commits cause corruption with dynamic resolution changes

Bug: 10192531
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
msm_fb: display: Program TILE video frame size in dma ISR

Since, video tile frame size register is single buffered, its
value takes effect as soon as it is programmed. Single buffered
registers like this should be configured very close to the vsync
to prevent issues like flicker or artifacts.
Program this register in dma ISR to prevent flickers and IOMMU
page faults.

Change-Id: Ifa770e4b4f29d6e4070e51388043422cc60e5872
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
msm: vidc: estimate min_dpb for smooth streaming mode

In case of smoothstreaming:
[1] get dpb requirement for the firmware
[2] get count in resource resource tracker
Use higher of the above

b/10192531

Signed-off-by: Deepak Verma <dverma@codeaurora.org>
Signed-off-by: Praveen Chavan <pchavan@codeaurora.org>
Revert "msm_fb: display: Program TILE video frame size in dma ISR"

This reverts commit a93ad3db3348fd7ffd0a1677911fd9edfc291090.
Bug: 10192531

Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>