[mips] Expand pseudo instructions before they are emitted in
MipsCodeEmitter.cpp.

JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not
called when the old JIT is used.

This fixes the following tests which have been failing on
llvm-mips-linux builder:

LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll
LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll
LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll
LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll
LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
LLVM :: ExecutionEngine__hello2.ll
LLVM :: ExecutionEngine__stubs.ll
LLVM :: ExecutionEngine__test-branch.ll
LLVM :: ExecutionEngine__test-call.ll
LLVM :: ExecutionEngine__test-common-symbols.ll
LLVM :: ExecutionEngine__test-loadstore.ll
LLVM :: ExecutionEngine__test-loop.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174912 91177308-0d34-0410-b5e6-96231b3b80d8
[Support][Compiler] Add LLVM_HAS_VARIADIC_TEMPLATES.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174913 91177308-0d34-0410-b5e6-96231b3b80d8
BBVectorize: Omit unnecessary entries in PairableInstUsers

This map is queried only for instructions in pairs of pairable
instructions; so make sure that only pairs of pairable
instructions are added to the map. This gives a 3.5% speedup
on the csa.ll test case from PR15222.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174914 91177308-0d34-0410-b5e6-96231b3b80d8
BBVectorize: Don't over-search when building the dependency map

When building the pairable-instruction dependency map, don't search
past the last pairable instruction. For large blocks that have been
divided into multiple instruction groups, searching past the last
instruction in each group is very wasteful. This gives a 32% speedup
on the csa.ll test case from PR15222 (when using 50 instructions
in each group).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174915 91177308-0d34-0410-b5e6-96231b3b80d8
Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
DIBuilder: make the return type of createBasicType more specific

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174924 91177308-0d34-0410-b5e6-96231b3b80d8
[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.
Part of rdar://12470373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
Update error message due to previous commit, r174926.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174927 91177308-0d34-0410-b5e6-96231b3b80d8
ARM NEON: Handle v16i8 and v8i16 reverse shuffles

Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
Cost model: Add check for reverse shuffles to CostModel analysis

Check for reverse shuffles in the CostModel analysis pass and query
TargetTransform info accordingly. This allows us we can write test cases for
reverse shuffles.

radar://13171406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174932 91177308-0d34-0410-b5e6-96231b3b80d8
ARM cost model: Add vector reverse shuffle costs

A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad
word).

radar://13171406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174933 91177308-0d34-0410-b5e6-96231b3b80d8
Check type for legality before forming a select from loads.

Sorry for the lack of a test case.  I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later.

I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174934 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the updating of LiveIntervals after splitting a critical edge. PHI operand
live ranges should always be extended, and the only successor that should be
considered for extension of other ranges is the target of the split edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174935 91177308-0d34-0410-b5e6-96231b3b80d8
Add blocks to the LiveIntervalAnalysis RegMaskBlocks array when splitting
a critical edge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174936 91177308-0d34-0410-b5e6-96231b3b80d8
Renumber SlotIndexes locally when a new block is inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174937 91177308-0d34-0410-b5e6-96231b3b80d8
Add a hidden option to PHIElimination to split all critical edges. This is
particularly useful for catching issues with architectures that have exotic
terminators like MIPS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174938 91177308-0d34-0410-b5e6-96231b3b80d8
Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174944 91177308-0d34-0410-b5e6-96231b3b80d8
Don't consider definitions by other PHIs live-in when trimming a PHI source's
live range after inserting a copy at the end of a block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174945 91177308-0d34-0410-b5e6-96231b3b80d8
Support string attributes in the AttrBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174948 91177308-0d34-0410-b5e6-96231b3b80d8
Use the AttributeSet as the 'key' to the map instead of the 'raw' pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174950 91177308-0d34-0410-b5e6-96231b3b80d8