ENGR00265061 System hang when running the game lsh.emu.apk

The game will creat a lot of hr timer, and make cpu tick broadcast
bit not been clear all time. It will cause user space thread not
been scheduled.

Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>
ENGR00266312 mx6dl: add i2c4 bus support for sabresd/auto, arm2 platforms

imx6dq have 3 i2c controllers and 5 ecspi,imx6dl have 4 i2c4
controllers and 4 ecspi. imx6dl i2c4 clock source is routed
from pll3 through to ecspi_root gate.

Add i2c4 bus support for sabresd/auto, and arm2 platforms.

Signed-off-by: Fugang Duan  <B38611@freescale.com>
ENGR00181680-1 No audio when play 3 streams after 3~10 seconds sometimes

sdma: bd is bufferable dma buffer, interrupt handler can not get correct
      data after sdma script updated. Which will cause there is no interrupt
      after failed period number times in the interrupt handler.
This is a workaround.

Signed-off-by: b02247 <b02247@freescale.com>
ENGR00181680-2 No audio when play 3 streams after 3~10 seconds sometimes

sdma: bd is bufferable dma buffer, interrupt handler can not get correct
      data after sdma script updated. Which will cause there is no interrupt
      after failed period number times in the interrupt handler.
This is a workaround.

Signed-off-by: b02247 <b02247@freescale.com>
ENGR00240112-1 caam: fix user space crypto API support.

This patch fix the CAAM support for Crypto User Space API support.
in the dma_map_sg_chained() function, the chained mode will loop
until the scatter list end, but when the scatter list end, it will
return null and orignal code will set this to the sg list point
used by dma_sync, so it will panic.

When do chain dma, use a tmp do going through the list.

Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
ENGR00240112-2 crypto: caam: add ecb(aes) crypto algorithm to caam.

add ecb(aes) support for caam algorithm, the caam H/W
support both ecb and cbc, add the algorithm into template.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
ENGR00267089 mx6: Amend the definitions of ANADIG_ANA_MISC2_REGx_STEP_TIME_MASK

Correct the definitions of ANADIG_ANA_MISC2_REG0_STEP_TIME_MASK and
ANADIG_ANA_MISC2_REG2_STEP_TIME_MASK to 0x03000000 and 0x30000000 respectively

Signed-off-by: Peter Chan <B18700@freescale.com>
ENGR00269604 Fix the set clock-rate for audio & video

There is single method to set clock-rate for both audio and video pll-s
in i.MX6q clock system implementation. That's possible due to they have
similar set of registers with a different bases. But there is also one
common register: CCM_ANALOG_MISC2, which contains post-dividers.

In current implementation, independently of whether audio or video clock
is going to be set, the mask 0xc0000000 is applied to MISC2 register.
This means, that if the audio clock rate is changed, the video clock
post-dividers possibly will be corrupted.

This patch fixes the issue described above.

Signed-off-by: Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>
ENGR00269935 Fix the build break

Add missing parenthesis

Signed-off-by: Mahesh Mahadevan <Mahesh.Mahadevan@freescale.com>