M2: camera: front sensor: run VFE in turbo mode as with back sensor
M2: camera: vfe: start vfe at 320000000
M2: camera: vfe: no more fake vfe clk rate
M2: camera: vfe: serialize ihist, cs, and rs stats operations using spinlocks

Also ratelimit some error messages.  They were overwhelming the ring
buffer and causing reboots, makingn debugging difficult.
M2: Request the correct ab/ib values for camera.

Various camera usecases show up bus overflows under
regression. Request right ab/ib values to ensure
camera has required bandwidth.

Increased ab, ib values for 8960 pro to run mmfab
at turbo

Change-Id: I1477fae2f0f6081e943d97ee0ffe9d17198a9b7e
Signed-off-by: Nishant Pandit <npandit@codeaurora.org>
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
M2: camera: Enable pixel line buffer for ispif.

Enable pixel line buffer for ispif to handle fast incoming
data. This provides cusion to dowmstream components such as vfe
and helps in preventing UB buffer overflows.

Change-Id: I0c2a0f8241e08d6cf39732db4ee05b34975b1557
Signed-off-by: Nishant Pandit <npandit@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
M2: camera: Disable software override for axi wm priority.

Remove the software override for write master priority because
hardware assigns priority to write masters based on data rate.

Change-Id: If16b54f05d41a2d78606ae21983aa3248eb2b1a3
Signed-off-by: Nishant Pandit <npandit@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
M2: camera: Enable CAMIF SOF in case of non dual camera usecase.

When Dual camera usecase is enabled, the ISPIF PIX SOF is enabled
by default to synchronize with the RDI interfaces.
But in non dual camera usecases, use CAMIF SOF IRQ to increment
the frame IDs being embedded inside the output frames.
Sometimes the SOF IRQs of frame 'n' is clubbed along with the
Output IRQs of the frame 'n-1'. Thus although the output IRQs
are supposed for frame 'n-1' it results in a frame ID of 'n' which
will cause incorrect behaviour downstream. Correct this behaviour
by checking the SOF and Output status bits in the IRQ Mask and
adjust the frame ID accordingly.

*detule: Also add similar checks for camif + stats irqs (as in upstream
driver)

CRs-Fixed: 481721
Change-Id: If7a9db2337febf10e89d44c58b9d980d874c69b6
Signed-off-by: Sai Kumar Sanagavarapu <ssanagav@codeaurora.org>
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
M2: camera: reset internal variables on reset interrupt
M2: camera: Recovery through camif stop and overall reset.

Add recovery mechanism in case of bus overflow. As part of the
recovery, stop the CAMIF, reset the VFE and reload the AXI
write masters and then restore the IRQ settings to VFE.

Change-Id: Iba6576777f05135cc13c1ee0c9db764d35c7282a
Signed-off-by: Kevin Chan <ktchan@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
M2: camera: Add recovery routine for live snapshot.

During live snapshot, if bus overflow happen, recovery routine will
kick in and reset the hardware. At this point, the live snapshot
might not be completed and application will continue to wait for
the snapshot to complete. This change adds the logic to restart
the snapshot process after recovery is completed.

*detule: we don't use Live Snapshot.  Mangle the patch, and only port
recovery_active pertinent code.

Change-Id: I9ba0a27ce53eb008a4af8d65a3f37a7cded03559
Signed-off-by: Kevin Chan <ktchan@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
M2: camera: Move halt logic in case of overflow to ISR.

Move the halt logic which includes AXI HALT and CAMIF Disable
to ISR to start the recovery mechanism sooner.
Add some protection in case of liveshot.

*detule: Again, omit liveshot lines.

Change-Id: I28ec462474524c0064cd7ecd4f77801cd494e514
Signed-off-by: Kevin Chan <ktchan@codeaurora.org>
Signed-off-by: Praveen Ac <praveenac@codeaurora.org>
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
M2: msm: Enable MSM_IOMMU for MACH_M2

And enjoy the free ram!
M2: msm: Enable IOMMU_GPU_SYNC

1. We need this to run with the new QdevNet adreno blobs.

2. HACK: prevent APPS side locking;  it's aggrevating the modem wdog.
Not sure why this happens, perhaps cpuidle, or preemption is
somehow responsible for the lock being held longer than anticipated.

3. Result is: serialized GPU-GPU acess to the context registers.
Apparently this is all that is needed to be able to use the QdevNet
adreno blobs.
M2: msm: grow MM heap size for the iommu use case

From 56 to 96 MB.

Too small of a heap and we get vidc induced iommu pagefaults when
recording 1080p video with the rear camera.

Change-Id: I70f2a1e76bda98c671ede22592ce564ce5fcd628