mach-exynos: Exynos 5410 clocking support
mach-exynos: Add Exynos 5410 bus traffic shaper
mach-exynos: Add Exynos 5410 adaptive support voltage
devfreq: Add Network-on-Chip bandwidth monitoring probe
devfreq: Add Exynos 5410 bus/int DVFS drivers
devfreq: Add Simple Usage devfreq governor
crypto: Samsung Advanced Crypto Engine (ACE) driver updates
dma: ARM PL330 DMA controller updates
ARM: 7485/1: EXYNOS: use SGI0 to wake secondary CPUs

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Conflicts:

	arch/arm/mach-exynos/platsmp.c
ARM: 7536/1: smp: Formalize an IPI for wakeup

Remove the offset from ipi_msg_type and assume that SGI0 is the
wakeup interrupt now that all WFI hotplug users call
gic_raise_softirq() with 0 instead of 1. This allows us to
track how many wakeup interrupts are sent and also removes the
unknown IPI printk message for WFI hotplug based systems.

Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: gic: use a private mapping for CPU target interfaces

The GIC interface numbering does not necessarily follow the logical
CPU numbering, especially for complex topologies such as multi-cluster
systems.

Fortunately we can easily probe the GIC to create a mapping as the
Interrupt Processor Targets Registers for the first 32 interrupts are
read-only, and each field returns a value that always corresponds to
the processor reading the register.

Initially all mappings target all CPUs in case an IPI is required to
boot secondary CPUs.  It is refined as those CPUs discover what their
actual mapping is.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
ARM: gic: add CPU migration support

This is required by the big.LITTLE switcher code.

The gic_migrate_target() changes the CPU interface mapping for the
current CPU to redirect SGIs to the specified interface, and it also
updates the target CPU for each interrupts to that CPU interface
if they were targeting the current interface.  Finally, pending
SGIs for the current CPU are forwarded to the new interface.

Because Linux does not use it, the SGI source information for the
forwarded SGIs is not preserved.  Neither is the source information
for the SGIs sent by the current CPU to other CPUs adjusted to match
the new CPU interface mapping.  The required registers are banked so
only the target CPU could do it.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
ARM: mm: define cache levels for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
coherency requirements. In order to select which cache levels must be
cleaned and invalidated, a new kernel cache maintenance API must be
added to the cpu_cache_fns structure of pointers.

This patch adds flush_dcache_level(level) to the ARM kernel cache
maintenance API.

This function cleans and invalidates all data cache levels up to the one
passed as an input parameter.

The cpu_cache_fns struct reflects this change by adding a new function
pointer that is initialized by arch specific assembly files.

The preferred cached level to be cleaned/invalidated can be retrieved
using the function call:

flush_cache_level_cpu(void)

By default, this function returns -1 which causes all cache levels to
be cleaned and invalidated to main memory.

Architectures can override the cache level returned by default by
patching/defining the preferred cache level hook for the arch in
question.

By default, all existing archs do not instantiate any cache level function
pointer, and flush_dcache_level just falls back to flush_kern_all.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Vincent Guittot <vincent.guittot at linaro.org>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Colin Cross <ccross at android.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Amit Kachhap <amit.kachhap at linaro.org>
ARM: mm: v7 cache level operations

ARM v7 architecture introduces the concept of cache levels and registers
to probe and manage cache levels accordingly.

This patch adds v7 support for dcache level operations and defines a
preferred cache level hook that by default is set to Level of
Unification Inner Shareable (LoUIS).

Allowed cache levels are:
	-1: 	flush the entire cache system
	 0:	no-op
	 [1-7]  flush the corresponding data cache level

[LoUIS] has been chosen as preferred level since it represents the cache
levels which are not shared by CPUs in most of the current systems (i.e.
cache levels that are per-CPU as e.g. an integrated L1).

Power-down operations like hotplug and CPU idle require to clean/invalidate
only cache levels that are within the CPU power domain, and LoUIS reflects
this requirement properly in most of the systems.

To improve configurability and possibly optimize cache operations a DT binding
is in the making to allow platforms to define the preferred cache level in a
more flexible way.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Vincent Guittot <vincent.guittot at linaro.org>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Colin Cross <ccross at android.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Amit Kachhap <amit.kachhap at linaro.org>
ARM: kernel: update cpu_suspend code to use dcache level operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes the L2
unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced dcache level function. The HW cache level is retrieved
through the hook

flush_cache_level_cpu(void)

that returns the preferred data cache level to be flushed for the respective
architecture/platform.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Tested on an A15 dual-core cluster through CPU soft-reset.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Vincent Guittot <vincent.guittot at linaro.org>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Colin Cross <ccross at android.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
Cc: Amit Kachhap <amit.kachhap at linaro.org>
ARM: 7559/1: smp: switch away from the idmap before updating init_mm.mm_count

When booting a secondary CPU, the primary CPU hands two sets of page
tables via the secondary_data struct:

	(1) swapper_pg_dir: a normal, cacheable, shared (if SMP) mapping
	    of the kernel image (i.e. the tables used by init_mm).

	(2) idmap_pgd: an uncached mapping of the .idmap.text ELF
	    section.

The idmap is generally used when enabling and disabling the MMU, which
includes early CPU boot. In this case, the secondary CPU switches to
swapper as soon as it enters C code:

	struct mm_struct *mm = &init_mm;
	unsigned int cpu = smp_processor_id();

	/*
	 * All kernel threads share the same mm context; grab a
	 * reference and switch to it.
	 */
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;
	cpumask_set_cpu(cpu, mm_cpumask(mm));
	cpu_switch_mm(mm->pgd, mm);

This causes a problem on ARMv7, where the identity mapping is treated as
strongly-ordered leading to architecturally UNPREDICTABLE behaviour of
exclusive accesses, such as those used by atomic_inc.

This patch re-orders the secondary_start_kernel function so that we
switch to swapper before performing any exclusive accesses.

Cc: <stable@vger.kernel.org>
Cc: David McKay <david.mckay@st.com>
Reported-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Revert "UPSTREAM: ARM: Remove current_mm per-cpu variable"

This originally removed some not-needed code, but the recent A15 errata
workaround actually needs current_mm still around. So for bring this
code back for that reason.

This reverts commit 696cfa01f12ec85ac7122eb57d77c8598f79ff71.

BUG=chromium:226280
TEST=build kernel for daisy

Change-Id: Ie44c6bfea7137ca185eb568f9047bca39f3e1b5c
Signed-off-by: Olof Johansson <olofj@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47426
Reviewed-by: Doug Anderson <dianders@chromium.org>
BACKPORT: arm: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)

On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:

1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
   one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
   return code already).

The switch_mm() code includes a DMB operation since the IPI is only sent
to CPUs running the same ASID.

BUG=chromium:226280
TEST=There's unfortunately no simple test to trigger this bug, since it
normally manifests vaguely by random crashes or bad data later during
runtime. General testing to make sure it doesn't add new problems (i.e,
BVT, regression suites) is the best approach, followed by observations
of crash rates from the field.

Change-Id: I8fa68bdac9594a90d29079244efa93750f4319e3
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47427
Reviewed-by: Doug Anderson <dianders@chromium.org>
temporary commit, >> don't fork or pull <<