Update defconfig
OMAP4: PM: work around for CPU1 onlining from OFF/OSWR state on older PPA

Originally detected in OMAP4430 ES2.3 HS samples, CPU1 crashes the
device upon calling PPA service DEFAULT_POR_NS_SMP(0x25).

Rootcause showed that cache maintenance operations required to be
performed before handing over control of CPU1 to HLOS, were incomplete
and not broadcasted from CPU0 to CPU1.

Kernel workaround for this is to use WFI to put CPU1 in OFF
state if CPU0 is not ready yet (this mechanism was in place in previous
versions of this code base but was meant to address a different need).
When putting CPU1 back to off, its internal MMU descriptors are reset
and sync'd with CPU0. CPU1 is brought online by later kernel subsystems.
Note: CPU0 power state is made to OFF for both OSWR and OFF modes.

This issue has been analysed to impact all OMAP4 non GP devices.

A config flag is introduced to allow platforms and distributions to
enable/disable if PPA version requirement is not met.

Change-Id: I82c5880ec2d9a98a54755dfbd01aa981cfed9852
[nm@ti.com, cileija@ti.com: improvements and rootcause support]
Signed-off-by: Carlos Leija <cileija@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com]
[wwang@ti.com: WA identification]
Signed-off-by: Wenbiao Wang <wwang@ti.com>

Conflicts:

	arch/arm/mach-omap2/Kconfig

Conflicts:

	arch/arm/mach-omap2/Kconfig
PM / Hibernate: Correct additional page calculation

The struct bm_block is allocated by chain_alloc(),
so it'd better counting it in LINKED_PAGE_DATA_SIZE.
ARM: hwcaps: add new HWCAP defines for ARMv7-A

Modern ARMv7-A cores can optionally implement these new hardware
features:

- VFPv4:
    The latest version of the ARMv7 vector floating-point extensions,
    including hardware support for fused multiple accumulate. D16 or D32
    variants may be implemented.

- Integer divide:
    The SDIV and UDIV instructions provide signed and unsigned integer
    division in hardware. When implemented, these instructions may be
    available in either both Thumb and ARM, or Thumb only.

This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never be set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.
mm: vmscan: check page order in isolating lru pages

Before attempting to take all pages in the order aligned region, check for
page order is added for minor optimization, since the pfn-based isolation
could be bypassed if the newly isolated page is no less than that region.

v1->v2 changes
1, the reason to add the check is described in change log,
2, the check is corrected,
3, comment for the check is corrected.

Thanks for all comments recieved.

Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: Michal Hocko <mhocko@suse.cz>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: David Rientjes <rientjes@google.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Hillf Danton <dhillf@gmail.com>
Revert "ARM: hwcaps: add new HWCAP defines for ARMv7-A"

This reverts commit 1dada5bd26607cbd03646bfe22bd534b1f0c9bb3.
ARM: hwcaps: use shifts instead of hardcoded constants

The HWCAP numbers are defined as constants, each one being a power of 2.
This has become slightly unwieldy now that we have reached 32k.

This patch changes the HWCAP defines to use (1 << n) instead of coding
the constant directly. The values remain unchanged.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: hwcaps: add new HWCAP defines for ARMv7-A

Modern ARMv7-A cores can optionally implement these new hardware
features:

- VFPv4:
    The latest version of the ARMv7 vector floating-point extensions,
    including hardware support for fused multiple accumulate. D16 or D32
    variants may be implemented.

- Integer divide:
    The SDIV and UDIV instructions provide signed and unsigned integer
    division in hardware. When implemented, these instructions may be
    available in either both Thumb and ARM, or Thumb only.

This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never be set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.

Signed-off-by: Will Deacon <will.deacon@arm.com>
mm: vmscan: recompute page status when putting back

If unlikely the given page is isolated from lru list again, its status is
recomputed before putting back to lru list, since the comment says page's
status can change while we move it among lru.

Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: David Rientjes <rientjes@google.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Hillf Danton <dhillf@gmail.com>
ARM: smp_twd: make sure timer is stopped before registration

On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.

The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.

Problem seen on VE (Cortex A5) and Tegra.

Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
ARM: Fix handling of pending IRQs at request time

When an interrupt is marked as pending, and then subsequently requested,
the interrupt is not delivered to the handler.  The pending status is
entirely ignored, and is left set.  The patch below ensures that this
pending status is acted upon while requesting the interrupt.

This matters for two reasons:

1. If a suspend/resume cycle subsequently occurs, upon resume, we call
   check_irq_resend() while the interrupt layer is resuming.  This notices
   the pending IRQ, and tries to deliver it.

   However, at this time, the device drivers have not been resumed.  If
   the device is behind a serial bus which has not been configured, this
   can cause the kernel to hang or timeout while trying to access the
   inaccessible device.

2. If the device whose interrupt is being requested has already asserted
   its interrupt signal (and is holding it at its own active level) we
   need to process that interrupt to clear down the interrupt, to allow
   an edge-triggered interrupt input to respond to subsequent activations.

This can be caused by an interrupt occuring after free_irq(), the flow
handler noticing that it's been disabled, and recording an IRQS_PENDING
status, or by use of the probe_irq_*() functions.  Either gets us to the
state where we have IRQS_PENDING set, and remaining set indefinitely
after a subsequent request_irq() succeeds.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PM / Sleep: Fix race between CPU hotplug and freezer

commit 79cfbdfa87e84992d509e6c1648a18e1d7e68c20 upstream.

The CPU hotplug notifications sent out by the _cpu_up() and _cpu_down()
functions depend on the value of the 'tasks_frozen' argument passed to them
(which indicates whether tasks have been frozen or not).
(Examples for such CPU hotplug notifications: CPU_ONLINE, CPU_ONLINE_FROZEN,
CPU_DEAD, CPU_DEAD_FROZEN).

Thus, it is essential that while the callbacks for those notifications are
running, the state of the system with respect to the tasks being frozen or
not remains unchanged, *throughout that duration*. Hence there is a need for
synchronizing the CPU hotplug code with the freezer subsystem.

Since the freezer is involved only in the Suspend/Hibernate call paths, this
patch hooks the CPU hotplug code to the suspend/hibernate notifiers
PM_[SUSPEND|HIBERNATE]_PREPARE and PM_POST_[SUSPEND|HIBERNATE] to prevent
the race between CPU hotplug and freezer, thus ensuring that CPU hotplug
notifications will always be run with the state of the system really being
what the notifications indicate, _throughout_ their execution time.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
FixOTG clock and USB_DPLL
Add jRCU by Joe Korty
Revert "Add jRCU by Joe Korty"

This reverts commit cb310a6191972f1abcc50687ea29c7cb889df831.
CPU: Fix transition lateny
Enable PMD Clocks
Revert "FixOTG clock and USB_DPLL"

This reverts commit d733c9b089a04e1b9b17768501665395aada79e5.
Revert "ARM: smp_twd: make sure timer is stopped before registration"

This reverts commit 2dd54a99e8249b89ded9031b2dff6cb663820bfe.
Revert "mm: vmscan: check page order in isolating lru pages"

This reverts commit 8b180835746e92e77ae9587756b96c5feadc063d.