pcie_fpga: Add missing CS_N signal to the DDR SDRAM core.
Absence of this signal pin could lead to problems with DDR memory
calibration (in other words: it didn't work).
Also change adressing scheme from BANK_ROW_COLUMN to ROW_BANK_COLUMN.
Theoretically it should give better performance in our use case.
pcie_hdl: Add generic parameter in DDRs module for differentiating
between target devices.
I have enough of this shit. Code gets so messy when trying to make
educated guesses about family that it's not worth the trouble.
Just pass the parameter and generate appropiate code.
Plus, fix DDR core pin connections for Virtex6 version.
pcie_hdl: add missing CS_N signals for DDR cores.
pcie_hdl: Invert DDR core reset signal logic for A7 chips.