More complex clock gating example with two levels of clock gating.

test_regress/t:
  * t/t_gated_clk_2.pl: New file.
  * t/t_gated_clk_2.v: New file.
  * t/t_gated_clk_bad_2.pl: New file.
Fix simulation error when inputs and MULTIDRIVEN, bug634.
Merge branch 'gated-clock' of github.com:jeremybennett/verilator into gated-clock
Merge branch 'master' into gated-clock