* Rewrite of sampling clock generation to use only one set of counters,
* Sample the RX data bits in the MIDDLE of the bit to be more robust,
  Synchronise the sampling point to every start bit received

Also add "Optimize Here" Markers for later trials - ignore them for now

Original Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |229/256 ( 89%) |458 /896  ( 51%) |472 /640  ( 74%) |178/256 ( 70%) |20 /118 ( 17%)|

Resources for this commit:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |164/256 ( 64%) |339 /896  ( 38%) |376 /640  ( 59%) |119/256 ( 46%) |20 /118 ( 17%)|
Change uart_tx_count from integer to 3-bit integer,
change data sending from index into uart_tx_data_block to shift operation

Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |124/256 ( 48%) |277 /896  ( 31%) |231 /640  ( 36%) |90 /256 ( 35%) |20 /118 ( 17%)|
Change uart_rx_count from integer to 3-bit integer,
change data sending from index into uart_rx_data_block to shift operation

Convert shifting operation into function

Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |79 /256 ( 31%) |190 /896  ( 21%) |112 /640  ( 17%) |61 /256 ( 24%) |20 /118 ( 17%)|
Receive: Remove separate waiting state rx_send_block until data is fetched from system

This now taken care during  rx_wait_start_synchronise and  rx_get_start_bit states
Thus plenty of time for the system to get it's data

Advantage: Do not stall receiver and loose following data byte
 	   High risk: Stalling and starting inside a half-passed data block
                      --> All our syncronisation is gone to hell, VEERY BAAAD
Disadvantage: Discard old data byte which was not ACK'ed from system
	      (Can be lived with)

Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |77 /256 ( 30%) |179 /896  ( 20%) |110 /640  ( 17%) |60 /256 ( 23%) |20 /118 ( 17%)|
Change SYNC Reset to ASYNC reset

Saves some resources on Xilinx CoolRunner CPLD - effect/usefulness on FPGA unknown

Should pose no problem, because (in any decent design and when required :-) the Reset is
anyway synchronized and buffered in the toplevel.

Resources for Example CoolRunner II Project:
    |Macrocells     |Product Terms    |Function Block   |Registers      |Pins          |
    |Used/Tot       |Used/Tot         |Inps Used/Tot    |Used/Tot       |Used/Tot      |
    |77 /256 ( 30%) |129 /896  ( 14%) |100 /640  ( 16%) |58 /256 ( 23%) |20 /118 ( 17%)|
Document the interface
Correct formatting
Merge pull request #2 from sd2k9/cpld-optimizations

Cpld optimizations