core_logic: Add logic to hand over control of RAM bus

When executing an RPC operation, let the coprocessor have control of the
RAM bus.
core_logic: tri-state MISO during external reset

When the coprocessor is being reset by the in-system programmer, tri-state
the MISO line to avoid a bus contention.  This involves turning the
coprocessor reset into a bidirectional I/O to detect an external reset.
core_logic_test: Test coprocessor RAM access
core_logic: fix coprocessor RAM access logic