Major improvements in mem2reg and added "init" sync rules
Fixed async proc detection in mem2reg
Implemented $_DFFSR_ expression generator in verilog backend
Updated abc
Improved make rules for profiling and debugging
Added SigBit struct and refactored RTLIL::SigSpec::extract
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
Added more performance measurement infrastructure
Fixed O(n^2) performance bug in verilog preprocessor
Some driver changes/fixes
Renamed "placeholder" to "blackbox"
Updated command-reference-manual.tex
Started to write on AppNote 010: Verilog to BLIF
Progress on AppNote 010
Making prograss on Appnote 010
Added more generic _TECHMAP_ wire mechanism to techmap pass
Improved handling of initialized registers
Improved handling of techmap special wires
AppNote 010 progress