tcg-ppc64: Improve and_i32 with constant

Use RLWINM

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Improve and_i64 with constant

Use RLDICL and RLDICR.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use automatic implementation of ext32u_i64

The enhancements to and immediate obviate this.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Streamline qemu_ld/st insn selection

Using a table to look up insns of the right width and sign.
Include support for the Power 2.06 LDBRX and STDBRX insns.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement rotates

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement bswap64

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Handle constant inputs for some compound logicals

Since we have special code to handle and/or/xor with a constant,
apply the same to andc/orc/eqv with a constant.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement deposit

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us.  The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Cleanup i32 constants to tcg_out_cmp

Nothing else in the call chain ensures that these
constants don't have garbage in the high bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use TCGType throughout compares

The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly.  Rather than recomputing the TCGType enum from the arch64 bool,
pass around the original TCGType throughout.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use MFOCRF instead of MFCR

It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use ISEL for setcond

There are a few simple special cases that should be handled first.
Break these out to subroutines to avoid code duplication.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement movcond

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Use getauxval for ISA detection

Glibc 2.16 includes an easy way to get feature bits previously
buried in /proc or the program startup auxiliary vector.  Use it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement add2/sub2_i64

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement mulu2/muls2_i64

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>