alu: add immediate value logic into alu
regfile: asynchronous read
eab: add left shift
regfile: initalize to zero

This is just to avoid getting a ton of XXXX's in a verilog simulation.
Registers are not guaranteed to be anything after power on/soft reset
alu: explicit wire declaration
build: makefile updates
marmux: fix word size problem with immediate value
shf: initial implementation
lc3: memory and higher level blocks

Lots o work on the interblock glue
gitignore: added
lc3: lots of overall work